IEEE Solid-States Circuits Magazine - Spring 2018 - 53

patterns that may have otherwise
deteriorated the perceived quality of
digitized audio and video communications. Subtractive dither means that
a dither signal is added to the input of
an ADC and subtracted from its output or vice versa [30]. It can be used
not only for its original purpose but
also to background calibrate ADCs.
Figure 15 shows a block diagram of an
early example [31]. It subtracts dither
from the input to a two-step ADC and
then adds the dither to the ADC output. Subtractive dither smooths out
the ADC transfer function, greatly
improving the differential nonlinearity and the spurious-free dynamic
range. However, if the dither is not
completely removed at the output,
the dither residue can degrade the
signal-to-noise ratio (SNR). For example, nonzero dither residue can result
from gain error in the dither DAC and/
or the ADC. To avoid this limitation,
the digital output can be correlated
with the dither and used to adjust
the gain of the dither DAC so that the
amplitude of the dither injected in
the analog domain is chosen to cancel
the dither at the output [32], [33]. A
disadvantage of this technique is that
it reduces the maximum allowed Vin
because the dither occupies some of
the input range of the ADC. To maintain the same SNR as in the case without dither, the input-referred noise
of the ADC must be reduced, which
significantly increases its power dissipation when the SNR is not limited
by quantization noise.

converted back to the digital domain
by ADC 2. The output of ADC 2 is
multiplied by the accumulator output, which weights the bits pro duced by the second stage relative
to those produced by the first stage
to compensate for interstage gain
G 1,
error. The weighting factor is 1/ \
\
G
where 1 is a digital estimate of
G 1. Since the dither was subtracted
in the analog domain, it is added in
the digital domain to the accumulator output. The accumulator operates in a negative feedback loop and
G 1, forcing it to converge to
adjusts \
G 1. The operation of this loop will
be described in detail in Part 2 of
this series. The key point here is
that when the dither is injected at
the output of the ADSC, the required
resolution of the DAC increases
because each output of the ADSC
without dither leads to two inputs
to the DAC, assuming the dither is
binary valued.

To avoid this problem, Figure 17
shows that the dither can be injected at
the ADSC input [35]. The beauty of this
technique is that its implementation
has low complexity because it does
not increase the required DAC resolution. However, a disadvantage of this
technique is that it only calibrates for
inputs near the comparator thresholds in the ADSC. Another disadvantage is that this technique reduces
the redundancy or correction range
because introducing the dither at the
ADSC input is equivalent to changing
the thresholds of the comparators in
the ADSC. A similar technique was
used to spread out interstage-gain
errors in the frequency domain but not
to calibrate these errors, improving
the spurious-free dynamic range but
not the SNR [36].
Also, a redundant residue mode
can be used to background calibrate
for interstage gain errors [37]. Figure 18 shows two plots of the amplified

∧

ADSC1
Vin

Accumulator

DAC1
−

+
Σ

SHA
+

RNG

Dout
+

1/G1

ADC2

Figure 16: A two-step ADC with subtractive dither injected at the output of ADSC 1 to background calibrate for error in G 1 .

Subtractive Dither to Background
Calibrate for Interstage Gain Errors
Also, subtractive dither can be used
to background calibrate for interstage gain errors. Figure 16 shows
a block diagram of one approach in
which the dither is injected at the
output of the ADSC [28]. A related
technique was independently developed [34]. In this case, the dither is
converted to the analog domain by
the same DAC that operates on the
ADSC output. Then the dither is subtracted from the held input, multiplied by the interstage gain G 1, and

Dout

DAC1

ADSC1
RNG
Vin

Dither
DAC −
SHA
1

+
×

+
∧

Accumulator

1/G1

−µ

Σ
+

−
+

ADC2

Figure 17: A two-step ADC with subtractive dither injected at the input of ADSC 1 to background calibrate for error in G 1 .

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Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2018