IEEE Solid-States Circuits Magazine - Summer 2018 - 15

RF

R2
R1

A

-
+

B

Vin
IC 2

C1

Vout

R1
Vin

R4

R3

R2

Req

C2
R3

+-

+-

+
Vx
-

-+
R1

-+
R3

C1

C2

Vout

C2

R2
RF

Figure 15: A noninverting integrator.

but shifted by TCK /2, we conclude
that V1 · V2 + V3 · V4 + V5 · V6 + V7 · V8
is a signal with four times the input
frequency. The implementation is
shown in Figure 13(b). In reality, the
AND and OR gates are replaced
by NANDs.
The multiplication factor in Figures 12 and 13 is difficult to change,
a point of contrast to PLLs. Moreover,
delay mismatches among the stages
give rise to jitter and spurs.
The frequency multiplication
ability of DLLs can be exploited to
detect false locking. Consider the
architecture shown in Figure 14,
where an edge combiner multiplies
the frequency by a factor of N. This
result, fmult, is then divided by N and
compared to fin . With correct locking, fmult = N fin, leading to a low average value for the PFD output. In the
presence of false lock, on the other
hand, the total delay from CK in to
CK out is equa l to or g reater tha n
2TCK, and fmult < N fin . As a result, the
PFD output exhibits a higher average. The false lock flag can then be
used to adjust the tuning range of
the delay line so that the total delay
remains less than 2TCK.

Questions for the Reader
1) Suppose the up and down currents
in the charge pump of Figure 2(d)
have a mismatch of DI.How does
the DLL react to this mismatch?
2) The CP imperfections in Figure 2(d) create a periodic ripple

Figure 16: The Tow-Thomas biquad.

in Vcont . What is the effect of this
ripple on the output waveform?

Answers to Last Issue's Questions
1) Figure 15 shows a noninverting integrator. Derive the condition for the
elements so that the circuit acts as
an ideal integrator. What is the principal difficulty with this topology?
W e h a v e VB . VA = Vout R 1 /
(R 1 +R 2). Also, (Vin -VB)/R 3 + (Vout VB) /R 4 = VB C 2 s. Thus,
Vin = V
R1 C2 s
out
R1 + R2
R3
+ Vout c R 1
R1 + R2
R + R4
$ 3
- 1 m . (8)
R3 R4
R4
For ideal integration, the second
term on the right-hand side must
vanish, yielding R 2 /R 1 = R 4 /R 3 .
Another perspective provides
additional insight. If Vout is proportional to the integral of Vin,
t h e n s o a r e VA a n d VB . T h u s ,
I C2 = C 2 dVB /dt is also proportional to Vin, a condition that is met
only if the Norton equivalent of the
circuit in the dashed box reduces
to an ideal current source. Since
the Norton resistance is given by
R 3 | | R eq, we set R eq to - R 3 and
hence obtain R 2 /R 1 = R 4 /R 3 .
The pr i n c ip a l issue here is
that the circuit relies on equal
positive and negative feedback
factors and is prone to latch up
in the presence of component
mismatches.

2) Suppose the Tow -Thomas biquad of Figure 16 senses a large,
narrowband undesired channel at ~ = ~ -3dB . Which of the two
integrators produces greater voltage swings and hence experiences
more nonlinearity?
We have Vout /VX = - 1/ (R 3 C 2 s) .
The relative swings in the two
integrator outputs depend on the
component values. For example,
i f C 1 = C 2, R 2 = R 3 = R F , a n d
Q = 1, t h e n ~ n = 1/ (R 3 C 2) a n d
~ -3dB = 1.27~ n = 1.27/ (R 3 C 2) .
T h a t i s , | Vout /VX | = 1/1.27. I n
this case, the first integrator compresses first. If the undesired
channel occurs at 2~ -3dB, we have
| Vout /VX | = 1/2.54, observing even
a greater swing disparity.

References

[1] J. J. Spilker and D. T. Magill, "The delaylock discriminator: An optimum tracking
device," Proc. IEEE, vol. 49, pp. 1403-1416,
Sept. 1961.
[2] M. Bazes, "A novel precision MOS synchronous delay line," IEEE J. Solid-State Circuits, vol. 20, pp. 1265-1271, Dec. 1985.
[3] M. G. Johnson and E. I. Hudson, "A variable delay line PLL for CPU-coprocessor
synchronization," IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
[4] M. J. E. Lee, W. J. Dally, T. Greer, H. T. Ng,
R. Farjad-Rad, J. Poulton, and R. Senthinathan, "Jitter transfer characteristics of
delay-locked loops: Theories and design
techniques," IEEE J. Solid-State Circuits,
vol. 38, pp. 614-621, Apr. 2003.
[5] A. Homayoun and B. Razavi, "Relation
between delay line phase noise and ring
oscillator phase noise," IEEE J. Solid-State
Circuits, vol. 49, pp. 384-391, Feb. 2014.
[6] J. Sonntag and R. Leonowich, "A monolithic
CMOS 10 MHz DPLL for burst-mode data retiming," in Proc. Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 1990, pp. 194-195.

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