IEEE Solid-States Circuits Magazine - Summer 2018 - 18

The advantage of resilient designs is the ability
to mitigate the guard bands for both fast- and
slow-changing variations.
variations (e.g., temperature and
aging), resulting in higher average performance or energy efficiency. Since
commercial processors must satisfy
specific performance and power/
energy targets, performance or energyefficiency gains directly improve the
processor yield.
A key advantage of traditional
adaptive designs is the low design
overhead. The primary disadvantage
is the response-time requirement for
mitigating fast-changing variations,
such as high-frequency VDD droops.
Previous adaptive designs aimed to
reduce the impact of VDD droops on
path-timing margin by sensing the VDD
variation with an on-die monitor and
adjusting the FCLK during the droop
event [1], [5], [6]. Although these techniques may recover a small portion of

the timing-margin loss when the FCLK
is significantly faster than the resonant
droop frequency, the response time
limits the benefits across the DVFS
operating conditions. For this reason,
these designs still require FCLK or VDD
guard bands for fast-changing variations. In addition, the on-die monitors
require post-silicon calibration during
testing, resulting in higher test costs.

Resilient Designs
In contrast to traditional adaptive
designs that avoid timing-margin
failures in processor paths, resilient
timing-error detection and recovery
circuits [7]-[17] relax the responsetime constraint by allowing a dynamic
parameter variation to induce a pathtiming-margin failure. As illustrated in
Figure 2, a resilient design detects the

Clock Generator
PLL

Error

Error Control Unit

MEM

TRC

Data
Cache

Replay
Instruction
Cache
PC

Duty
Cycle

1/2 FCLK

clk_ref

Core

Latch

Error

Tuning Bits

CLK
EDS

EDS

...

TRC

Error

TRC

FIGURE 2: A resilient design with embedded EDS circuits and TRCs for error detection. PC:
program counter; IF: instruction fetch; DE: decode; RA: register access; EX: execute; MEM:
memory; X: exception; WB: write back; RF: register file; D: input data; Q: output data; CLK:
clock. (Image from [13].)

su m m e r 2 0 18

IEEE SOLID-STATE CIRCUITS MAGAZINE

timing-margin violation, isolates the
error from corrupting the architecture
state, and corrects the error through
a recovery technique (e.g., instruction
replay). As long as the resilient design
prevents the timing error from corrupting the architectural state of the
processor, error correction can occur
over multiple clock cycles. For this
reason, resilient circuits detect and
correct timing errors from both fastand slow-changing variations.
The resilient design in Figure 2
provides two separate circuits for error detection: 1) embedded errordetection sequential (EDS) circuits
[7]-[17] and 2) tunable replica circuits
(TRCs) [13]. The embedded EDS design replaces the receiving sequential
circuit in critical paths with an EDS
circuit to detect late timing transitions. The EDS circuit in Figure 2 is
a double-sampling with time-borrowing (DSTB) design [12], [13]. The shadow flip-flop (FF) and data-path latch
sample the input data (indicated as D
in Figure 2) on the rising and falling
clock edges, respectively. If the input
transitions between the rising and
falling clock edges (i.e., late), then the
latch output (indicated as Q in Figure 2)
and the FF output differ. An XOR logic
gate compares the latch and FF outputs to generate the error signal. The
error signals from each EDS circuit in a
pipeline stage drive an OR logic tree to
generate a single pipeline-error signal, which propagates to the writeback stage to invalidate the errant
instruction and to the error control unit
for error recovery.
A critical problem for some EDS
circuits [7]-[10] is the susceptibility to
data-path metastability when the input
arrives close to a rising clock edge,
resulting in the possibility of undetected errors. For DSTB, the data-path
latch operates as a pulsed latch, thus
eliminating data-path metastability
during a rising clock edge. Although
the shadow FF output can become
metastable during a rising clock edge,
the error path behaves similarly to a
traditional synchronizer circuit, thus
greatly simplifying the metastability problem. Even though the DSTB

IEEE Solid-States Circuits Magazine - Summer 2018

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