IEEE Solid-States Circuits Magazine - Summer 2018 - 22

Traditional adaptive designs with
on-die monitors and adaptive control
circuits effectively reduce the guard bands
for slow-changing variations.
is synchronized to the negative edge
of the TLD clock (clk_tld). The synchronized error (error_sync) drives
the clock divider to reduce the FCLK
by half and the ACU to execute an
algorithm for maintaining the 1/2
FCLK operation for the duration of the
VDD droop.
When a VDD droop occurs, the ACD
requires a 2.5-cycle response time
to adaptively change to 1/2FCLK (i.e.,
one cycle to detect the VDD droop
and 1.5 cycles to synchronize the
DVM ROOT error to reduce the FCLK by
half). Thus, the minimum target delay
for the TLD is 2.5 cycles. Post-silicon
TLD characterization with the on-die
frequency counter in Figure 6 results
in one TLD setting for all dies and operating conditions to satisfy the minimum response time for maximizing
the ACD benefits.
The on-die autocalibration circuit
directly interfaces with the DVM ROOT.
At the target FCLK and VDD, this circuit
initially calibrates the DVM ROOT timing margin to zero and then removes
a programmable number of delay
elements to provide a positive timing

margin for the DVM ROOT so the ACD
does not react to frequent small-magnitude VDD noise. The autocalibration
circuit enables in-field, low-latency
tuning of the DVM ROOT across a wide
range of FCLK, VDD, temperature, and
process conditions to maximize the
ACD benefits while eliminating the
costly overhead from tester calibration
[21]. This circuit is a critical feature for
deploying the ACD into high-volume
commercial processors.
The DVM diagnostic logic allows
timing-margin observability for the
DVM ROOT and the DVM with the clock
connected to clk_leaf (DVM LEAF). In
contrast to the DVM ROOT, the DVM LEAF
shares the same clock distribution as
the processor paths. For this reason,
the DVM LEAF captures the dynamic
delay variation in both the clock distribution and data path during a VDD
droop to accurately monitor criticalpath-timing-margin changes every
cycle. By disabling the clock divider,
the measurements in Figure 7 of the
DVM ROOT and DVM LEAF timing margins elucidate the TLD functionality
of providing a response time during

DVM Timing Margin (%)

8
Six-Cycle
Response Time

4
0

FCLK = 2.5 GHz
VDD = 0.9 V
10% VDD Droop

-4
-8

TLD = 2.4 ns
(Six Cycles at 2.5 GHz)

-12
-16

Root
Leaf

Clock Divider Disabled
0

8
10
Time (ns)

FIGURE 7: The measured DVMROOT and DVMLEAF timing margin versus time during a VDD droop
with the clock divider disabled to demonstrate the TLD response time. (Image from [21].)

su m m e r 2 0 18

IEEE SOLID-STATE CIRCUITS MAGAZINE

a 10% VDD droop. Although the ACD
response time requires only a minimum TLD of 2.5 cycles, the TLD calibration for this measurement applies
a 2.4-ns delay, with an FCLK of 2.5 GHz
(i.e., TCLK = 400 ps), to provide six
cycles of clock-data compensation.
The initial DVM ROOT timing-margin
reduction indicates the onset of a VDD
droop. The DVM LEAF timing margin,
however, does not degrade until six
cycles later, resulting from the TLD extending the clock-data compensation.
From previous test-chip measurements and simulations [19], [21], the
path clock-data compensation occurs
for the duration of the clock distribution delay (i.e., the TLD and global
clock distribution delays), regardless
of the VDD droop frequency.
In Figure 8, the conventional design operates at an FMAX of 2.95 GHz at
0.9 V. After injecting a 10% VDD droop,
the FMAX reduces to 2.56 GHz. Similar
to Figure 3, the shaded region in Figure 8 represents the FCLK guard band
for a 10% VDD droop in the conventional design. After enabling the ACD and
executing the autocalibration circuit at
a target FCLK of 2.95 GHz with an autocalibration margin of zero, the ACD
enables a higher FCLK and throughput
by detecting the droop and operating at 1/2 FCLK during the droop. The
maximum throughput gain of 10%
occurs at 2.83 GHz. A larger FCLK reduces the throughput because of the
increasing number of cycles at 1/2
FCLK. When the autocalibration circuit
applies a margin of one delay element,
the ACD recovers most of the throughput loss due to the 10% VDD droop for
a maximum throughput gain of 13%.
The autocalibration margin provides a
tradeoff between the throughput degradation at the calibrated FCLK and the
magnitude of the VDD droop mitigated
by the ACD.
As processors experience process
variations and operate across the DVFS
conditions, the autocalibration circuit
optimally configures the DVM ROOT to
maximize the ACD benefits. From 109
die measurements in Figure 9, the autocalibrating ACD recovers 100% of
the throughput loss in a conventional

IEEE Solid-States Circuits Magazine - Summer 2018

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