IEEE Solid-States Circuits Magazine - Summer 2018 - 25

ensuring coverage for all failure scenarios. The autocalibrating ACD retains the low design overhead of the
traditional adaptive design and resolves the response-time problem via
clock-data compensation to mitigate
the guard bands for high-frequency
VDD droops while avoiding the error
recovery in resilient designs. The autocalibration feature eliminates the
costly overhead of tester calibration
for high-volume commercial processors. Looking forward, the unification
of VDD and FCLK regulation into a single
control loop enables infinite clock-data
compensation with intrinsic FCLK adaptation for dynamic variation tolerance.

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About the Author
Keith A. Bowman (kbowman@qti
.qualcomm.com) is a principal engineer and manager in the Processor
Research Team at Qualcomm Technologies, Inc. in Raleigh, North Carolina.
He pioneered the invention, design,
and test of Qualcomm's first commercially successful circuit for mitigating the adverse effects of supply
voltage droops. He received his Ph.D.
degree from the Georgia Institute of
Technology, Atlanta, and worked at
Intel, Hillsboro, Oregon, for 12 years.
He has published more than 75 technical conference and journal papers,
received 15 patents, and presented
more than 35 tutorials on variationtolerant circuit designs. He currently
serves on the International Solid-State
Circuits Conference Technical Program Committee.

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IEEE Solid-States Circuits Magazine - Summer 2018

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