IEEE Solid-States Circuits Magazine - Summer 2018 - 36

Channel

Serializer

Tx
Data

N Bits

ADC

DSP

Rx
Data

CTLE and VGA
Ref
CLK

PLL

Tx
CLK

Rx
CLK

CDR

Figure 1: A high-speed serial link transceiver with an ADC-DSP receiver. CLK: clock; PLL: phase locked loop; Rx: receiver; Tx: transmitter.

improved area and power offered from
complementary metal-oxide-semiconductor (CMOS) scaling. However, the
power dissipation of both the highspeed ADC and the subsequent digital
equalizer is a major problem and an
active research area. This article provides an overview of ADC-based serial links with discussion on common
implementations and challenges in
the ADC, digital equalizer, and analog
front-end (AFE) design.

ADC Resolution Requirements
and Topologies
The required ADC resolution is a
function of the channel loss, amount
of transmitter and receiver front-end
equalization, modulation scheme,
and the overall required bit error
rate (BER). While previous PAM-2
serial links have required a raw BER
of 10 -12 or lower, this is often difficult to meet in PAM-4 systems due
to the lower signal-to-noise ratio.
Thus, PAM-4 systems often employ
forward error correction (FEC) that
requires only a raw input BER near
10 -4 to achieve an overall corrected
BER lower than 10 -18 [1].
A key difference between analog
and ADC-based serial link receivers
is the quantization noise introduced
by the ADC. This quantization noise
must be accurately modeled to select the necessary ADC resolution.
Figure 2(a) shows how this quantization noise is shaped by the digital
FFE. To include this effect in system
modeling, the quantization noise
probability density function (PDF)
at the ADC output is scaled by the

s u m m E r 2 0 18

different FFE coefficients, and the resulting PDFs are convolved together
to arrive at the final quantization
noise PDF. Assuming small ADC integral and differential nonlinearity, this
approach allows for direct convolution with other noise and distortion
PDFs to estimate the system margins.
The impact of the ADC effective
number of bits (ENOB) on the statistically combined 56-Gb/s PAM-4 voltage
margins for both a low- and high-loss
channel is shown in Figure 2(b). The
high-loss channel needs ENOBs between 3 and 4 b for the FEC BER target
and greater than 5 b to achieve a raw
BER 110 -12, whereas operating over
the low-loss channel requires only 3-b
ENOB for a 10 -12 raw BER. This motivates receiver architectures with configurable-resolution ADCs that allow for
a reduced number of bits to save power
in systems with lower-loss channels
[2]. Overall, the ADCs in typical PAM-4
systems are designed for 7-8-b resolution and achieve close to 5-6-b ENOB at
Nyquist [1]-[4]. This is relaxed in PAM-2
systems, where typical designs are
5-6-b resolution and achieve close to
4-4.5-b ENOB at Nyquist [5]-[7].
Figure 3 shows the common ADC
topologies used in these serial links,
which include flash, binary/multibit
search, and successive approximation
register (SAR). Flash ADCs employ
comparators at each reference level,
with a 6-b flash ADC requiring 63 comparators that simultaneously evaluate
over a single cycle. This allows for very
high-speed operation with relatively
low time-interleave factors between
four and eight. The main downside is

IEEE SOLID-STATE CIRCUITS MAGAZINE

the large comparator count, although
rectifying architectures can reduce
this [8]. Overall, flash ADCs are a reasonable choice for PAM-2, but the resolution is a bit low for PAM-4.
Binary or multibit search ADCs
combine desirable properties of flash
and SAR ADCs [9]. While conventional
binary search ADCs have the same
number of comparators as a flash
ADC, the architecture employs a binary search algorithm with the most
significant bit (MSB) comparator's output deciding which MSB-1 comparator is clocked, and so on. This results
in only the necessary comparators
evaluating, or six in a 6-b converter.
The binary search ADC avoids the digital-to-analog converter (DAC) settling
and logic delay present in SARs but is
slower than a flash due to the serial
comparator evaluation. Overall, this
is also a good choice for PAM-2 applications, but the area is often high for
PAM-4 applications.
An SAR ADC employs a binary search
conversion over multiple clock cycles.
The simplest implementations require
only one comparator per unit ADC,
whose decision adjusts a reference DAC
to make the full signal quantization in a
successive approximation manner, with
a 6-b converter clocking the comparator
six times. This results in a slower unit
ADC relative to flash or binary search,
with high-speed converters using higher
interleave factors of 32-128 [2], [10].
This is an excellent choice for 6-8-b resolution to support both PAM-2 and PAM-4,
and it is the dominant architecture for
PAM-4 ADC-based receivers. Given this,
the next section provides an overview of

IEEE Solid-States Circuits Magazine - Summer 2018

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