key ADC circuits in the context of a timeinterleaved SAR ADC. Note that many of the circuit concepts are also relevant to other ADC topologies. Key ADC Circuits Figure 4 shows a block diagram of a 32-way time-interleaved SAR ADC. The interleaving of the 32-unit ADCs is done in two stages due to the challenges in generating low-jitter and low-skew clock phases, with typical first-line interleaving factors chosen between four and 16. After the AFE, which often includes a continuous-time linear equalizer (CTLE) and variable-gain amplifier (VGA), there is a bank of eight first-line track-andhold (T/H) switches that sequentially Digital FFE Z -1 0.15 0.1 0.05 α1 Output PDF Z -1 fQ,FFE (q) Input PDF 0.15 fQ (q) sample the ADC input signal at timing offsets equal to the Nyquist-rate sampling period. Each sampled T/H output is then buffered to drive a bank of fourunit ADCs that perform a sequential second-line sampling operation and bit conversion at a rate equal to the overall ADC sampling rate divided by the interleave factor. α2 α3 0.05 0 -10 -6 -2 2 6 10 Quantization Noise (mV) 0 -10 -6 -2 2 6 10 Quantization Noise (mV) Quantization Noise PDF 0.8 0.6 0.4 0.2 0 -10 -6 -2 2 6 10 Quantization Noise (mV) 0.8 1/α3 fQ (q/α3)t 0.8 1/α2 fQ (q/α2) 1/α1 fQ (q/α1) 0.1 0.6 0.4 0.2 0 -10 0.6 0.4 0.2 0 -10 -6 -2 2 6 10 Quantization Noise (mV) -6 -2 2 6 10 Quantization Noise (mV) Scaled Noise PDFs Key Simulator Settings * Three-Tap Tx with One-Vpp Swing * CTLE/VGA Front End with 7.4-dB Peaking and 16-GHz BW * 400-mV ADC FSR * Digital 14-Tap FFE and One-Tap DFE * 3-mVrms ADC Input Noise * RJ = 300 fsrms (b) 0 37.2-dB Channel -2 0 -4 ADC ENOB 2 -6 3 Statistically 4 -8 5 Combined 6 PAM-4 -10 7 Voltage Margin 8 -12 -60 -40 -20 0 20 40 60 Voltage Margin (mV) 9.4-dB Channel -2 FEC Target BER (log10) 0 -5 -10 -15 -20 -25 -30 14 GHz Loss 9.4-dB -35 37.2-dB -40 -45 0 2 4 6 8 10 12 14 16 Frequency (GHz) BER (log10) S21 (dB) (a) FEC Target -4 ADC ENOB 2 -6 3 4 -8 5 6 -10 7 8 -12 -60 -40 -20 0 20 40 60 Voltage Margin (mV) (c) (d) Figure 2: (a) The modeling of quantization noise amplification through a digital FFE. (b) The frequency response of two electrical printed circuit board channels. A comparison of 56-Gb/s PAM-4 voltage bathtub curves with varying ADC ENOB for the (c) 37.2-dB loss channel and (d) 9.4-dB loss channel. BW: bandwidth; RJ: random jitter. IEEE SOLID-STATE CIRCUITS MAGAZINE su m m E r 2 0 18 37