IEEE Solid-States Circuits Magazine - Summer 2018 - 39

While the DAC thermal noise should
also be considered when setting the
total capacitance value, the overall
system noise is generally dominated
by the comparator and AFE.
The comparator makes a decision
on the DAC signal to generate the output bits that serve as the binary search
codes for the SAR logic that controls
the DAC. A typical StrongArm regenerative comparator is shown in Figure 6(b). Important considerations are
noise, offset, and metastability. Noise
and offset considerations generally set
the minimum comparator size. However, the brute-force design of a comparator for a given offset performance
leads to excessive power and area in
modern CMOS processes. Instead, the
comparator offset is often canceled in
the analog domain with either currentmode or capacitive DACs attached to
internal nodes or by using an additional parallel input differential

pair that is controlled by a DAC. The
comparator evaluation time consists
of an initial integration time to discharge the output nodes past the P-type
metal-oxide-semiconductor threshold
and an exponential regeneration time
where the equivalent cross-coupled
inverters operate in positive feedback
to amplify the input signal to a full
VDD value [12]. The regeneration time
dominates for small input signals, and
thus the regeneration time constant is
set to ensure the metastability error
rate is less than the target BER. Using an
SAR ADC metastability error model [13]
on a 32-way interleaved 8-b 32-GS/s
ADC, Figure 6(c) shows that a fast comparator with a small 6-ps regeneration
time constant allows the metastability
error rate to be relatively low. However,
a slower comparator with a 12-ps time
constant has a probability of a metastability error of several least significant bits that exceeds the target BER.

These metastability errors will propagate through the digital FFE and impact
the overall receiver BER. It is important
to note that these metastability events
are not easily visible with traditional
SNDR characterization techniques, as
shown in Figure 6(d), and it is critical
to characterize the comparator time
constant in the design phase and use
system models to predict the metastability error rate.
Finally, the SAR logic generates both
the comparator clock and the DAC control signals based on the comparator
output. A conventional synchronous
SAR ADC uses logic that generates an
internal clock operating at N + 1 times
the unit ADC sampling frequency to
allow for one tracking cycle and N-bit
conversion cycles. However, given
metastability considerations, each cycle should be timed to satisfy the worstcase comparator input that will occur
only once in the multibit conversion.

First-Line Bootstrapped T/H, Source Follower Buffer, and Second-Line Switch
VDD
M2

T/H
CLK

Φ2

VOUT

BS
Hold

M1
VG

VIN

VS
CDAC

Source Follower
Buffer
(a)

Bootstrapped T/H
VDD

MN 2
COS

Equivalent Buffer/Second-Line Switch Circuit
RON
V
V

MP 2
Φ

MP 3
VGSgm1

MP 1
MN T 4

MN1
Vin

OUT

MN 3S
MN 3

Second-Line
Switch

rO1//rO2

CDAC

MN 4
Vout

MNSW
Main SW
(b)

(c)

Figure 5: (a) A first- and second-line switch circuitry, (b) bootstrapped T/H, and (c) source follower buffer and second-line switch model.

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IEEE Solid-States Circuits Magazine - Summer 2018

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