IEEE Solid-States Circuits Magazine - Summer 2018 - 43

A key difference between analog and ADC-based
serial link receivers is the quantization noise
introduced by the ADC.
ficiency [19]. Other FFE power-saving
techniques include the use of canonical signed digit arithmetic and the tapering of the coefficient range for taps
far from the main tap.
A DFE is a nonlinear equalizer that
directly subtracts ISI based on previous symbol decisions. Unlike an FFE,
meeting the critical timing paths in
DFE is difficult due to the feedback
paths and the inability to perform
pipelining in a straightforward manner. Figure 9(a) shows a conceptual
full-rate implementation that has all
of the summers, a multiplier, and a
digital comparator in the critical timing path, which should be completed
in one unit interval (UI) or symbol
time. This conceptual implementation has a loop critical path delay
that is significantly longer than the
iteration bound defined as the ratio

converged equalizer tap coefficients
of a per-slice adaptive equalizer [18].

Digital Equalization
The most common serial link digital
equalization architectures consist of a
multitap FFE that is optimized to cancel precursor ISI and concentrate the
postcursor ISI for effective cancellation by a subsequent DFE. As shown in
Figure 8, the FFE is a symbol-by-symbol linear equalizer with an architecture independent of the modulation
format. The digital FFE is implemented
in a parallel manner with a slice count
that often matches or exceeds the ADC
time-interleaving factor. An absence of
any feedback stages allows for digital
pipelining to easily meet high-speed
timing constraints. This relaxed timing allows for power supply scaling
techniques to improve FFE power ef-

Y (n-N )
Y (n-1)
Precomputation Section

αN

α1

-α2
α2

-αN

Z -N

2N-1

-α2

Y (n)

-α1

N-UI Loop Timing Path

1-UI Loop Timing Path

2N : 1 Mux

α2

Z -1

1
.

involves digitally monitoring the ADC
peak output and correcting it in the analog domain to match the ADC full-scale
range (FSR). In a flash ADC, this is commonly achieved by adjusting the comparator thresholds and by VGA stages
[16]. In SAR ADCs, typical approaches
included adjusting the DAC reference
voltages [17] or introducing additional
programmable DAC capacitors [6]. Further digital fine-gain calibration is also
possible in the DSP.
Bandwidth errors are due to similar unit ADC device mismatches and
also layout asymmetries. A bruteforce way to address this is to simply
design the signal path with sufficient
bandwidth, such that any variations
don't translate into major differences
in the effective unit ADC pulse response. This motivates the use of
bandwidth extension techniques,
such as shunt inductive peaking in
the AFE and the use of neutralization
capacitors in unit ADC preamplifiers [18]. An effective way to digitally compensate for these bandwidth
errors is provided with the digital
equalizer's parallel implementation,
where the parallel slice number is
often equal to or exceeds the ADC's
time-interleave factor. This allows
for the treatment of each unit ADC
as a unique channel, and the perchannel adaptation of the digital
FFE and decision feedback equalizer
(DFE) taps to independent values
optimized for the specific effective
channel bandwidth [18].
Finally, skew errors are dominated by device mismatches and layout
asymmetries in the multiphase clock
generation and distribution to the
first-line T/H switches. Skew error
calibration is possible with per-phase
digitally adjustable delay cells in the
clock distribution buffers [6] and by
using phase interpolators with independent clock-and-data-recovery
control codes. Similar to bandwidth
errors, these skew errors will cause
each unit ADC channel to generate a
pulse response with a slightly different ISI characteristic. Thus, an effective approach to detect skew errors
is to monitor the differences in the

Figure 10: The technique of loop unrolling applied to an N-tap PAM-2 digital DFE.

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IEEE Solid-States Circuits Magazine - Summer 2018

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