IEEE Solid-States Circuits Magazine - Summer 2018 - 47

H. Zhang, and K. Chang, "A 56-Gb/s PAM4
wireline transceiver using a 32-way timeinterleaved SAR ADC in 16-nm FinFET,"
IEEE J. Solid-State Circuits, vol. 52, no. 4,
pp. 1101-1110, Apr. 2017.
[2] P. Upadhyaya, C. F. Poon, S. W. Lim, J.
Cho, A. Roldan, W. Zhang, J. Namkoong,
T. Pham, B. Xu, W. Lin, H. Zhang, N. Narang, K. H. Tan, G. Zhang, Y. Frans, and
K. Chang, "A fully adaptive 19-to-56 Gb/s
PAM-4 wireline transceiver with a configurable ADC in 16 nm FinFET," in Proc.
2018 IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, pp. 108-109.
[3] K. Gopalakrishnan, A. Ren, A. Tan, A. Farhood, A. Tiruvur, B. Helal, C.-F. Loi, C. Jiang, H. Cirit, I. Quek, J. Riani, J. Gorecki,
J. Wu, J. Pernillo, L. Tse, M. Le, M. Ranjbar,
P.-S. Wong, P. Khandelwal, R. Narayanan,
R. Mohanavelu, S. Herlekar, S. Bhoja, and
V. Shvydun, "A 40/50/100 Gb/s PAM-4 Ethernet transceiver in 28 nm CMOS," in Proc.
2016 IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, pp. 62-63.
[4] D. Cui, H. Zhang, N. Huang, A. Nazemi, B.
Catli, H. Rhew, B. Zhang, A. Momtaz, and
J. Cao, "A 320 mW 32 Gb/s 8b ADC-based
PAM-4 analog front-end with programmable gain control and analog peaking in 28
nm CMOS," in Proc. 2016 IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, pp. 58-59.
[5] S. Rylov, T. Beukema, Z. Toprak-Deniz,
T. Toifl, Y. Liu, A. Agrawal, P. Buchmann,
A. Rylyakov, M. Beakes, B. Parker, and M.
Meghelli, "A 25 Gb/s ADC-based serial line
receiver in 32 nm CMOS SOI," in Proc. 2016
IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers, pp. 56-57.
[6] A. Shafik, E. Zhian Tabasy, S. Cai, K. Lee,
S. Hoyos, and S. Palermo, "A 10 Gb/s hybrid ADC-based receiver with embedded
analog and per-symbol dynamically-enabled digital equalization," IEEE J. SolidState Circuits, vol. 51, no. 3, pp. 671-685,
Mar. 2016.
[7] B. Zhang, A. Nazemi, A. Garg, N. Kocama n, M. R. A h madi, M. K ha npour, H.
Zhang, J. Cao, and A. Momtaz, "A 40 nm
CMOS 195 mW/55 mW dual-path receiver
AFE for multi-standard 8.5-11.5 Gb/s serial links," IEEE J. Solid-State Circuits, vol.
50, no. 2, pp. 426-439, Feb. 2015.
[8] L. Wang, Y. Fu, M. LaCroix, E. Chong, and
A. C. Carusone, "A 64 Gb/s PAM-4 transceiver utilizing an adaptive threshold
ADC in 16 nm FinFET," in Proc. 2018 IEEE
Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 110-111.
[9] S. Cai, E. Z. Tabasy, A. Shafik, S. Kiran, S.
Hoyos, and S. Palermo, "A 25 GS/s 6b TI
two-stage multi-bit search ADC with softdecision selection algorithm in 65 nm
CMOS," IEEE J. Solid-State Circuits, vol. 52,
no. 8, pp. 2168-2179, Aug. 2017.
[10] J. Cao, D. Cui, A. Nazemi, T. He, G. Li, B.
Catli, M. Khanpour, K. Hu, T. Ali, H. Zhang,
H. Yu, B. Rhew, S. Sheng, Y. Shim, B.
Zhang, and A. Momtaz, "A transmitter and
receiver for 100 Gb/s coherent networks
with integrated 4 × 64 GS/s 8b ADCs and
DACs in 20 nm CMOS," in Proc. 2017 IEEE
Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 484-485.
[11] M. Dessouky and A. Kaiser, "Input switch
configuration suitable for rail-to-rail operation of switched op amp circuits," Electron. Lett., vol. 35, no. 1, pp. 8-10, Jan.
1999.
[12] J. Kim, B. Leibowitz, J. Ren, and C. Madden, "Simulation and analysis of random
decision errors in clocked comparators,"
IEEE Tran. Circuits Syst. I, vol. 51, no. 3,
pp. 671-685, Mar. 2016.

[13] S. Cai, A. Shafik, S. Kiran, E. Z. Tabasy, S.
Hoyos, and S. Palermo, "Statistical modeling of metastability in ADC-based serial I/O receivers," in Proc. 2014 IEEE 23rd
Conf. Electrical Performance Electronic
Packaging and Systems, pp. 39-42.
[14] S.-W. M. Chen and R. Brodersen, "A 6-bit
600-MS/s 5.3-mW asynchronous ADC in
0.13-µm CMOS," IEEE J. Solid-State Circuits,
vol. 41, no. 12, pp. 2669-2680, Dec. 2006.
[15] S. Kiran, A. Shafik, E. Z. Tabasy, S. Cai, K.
Lee, S. Hoyos, and S. Palermo, "Modeling
of ADC-based serial link receivers with
embedded and digital equalization," to be
published.
[16] J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D.
Pi, B. Raghavan, H. Pan, I. Fujimori, and A.
Momtaz, "A 500 mW ADC-based CMOS AFE
with digital calibration for 10 Gb/s serial
links over KR-backplane and multimode
fiber," IEEE J. Solid-State Circuits, vol. 45,
no. 6, pp. 1172-1185, June 2010.
[17] L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Brandli, M. Kossel, T.
Morf, T. M. Andersen, and Y. Leblebici, "A
3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm
digital SOI CMOS," IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec.
2013.
[18] A. Varzaghani, A. Kasapi, D. Loizos, S.H. Paik, S. Verma, S. Zogopoulos, and S.
Sidiropoulos, "A 10.3-GS/s, 6-bit flash
ADC for 10G Ethernet applications," IEEE
J. Solid-State Circuits, vol. 48, no. 12, pp.
3038-3048, Dec. 2013.
[19] T. Toifl, P. Buchmann, T. Beukema, M.
Beakes, M. Brandli, P. A. Francese, C. Menolfi, M. Kossel, L. Kull, and T. Morf, "A 3.5
pJ/bit 8-tap-feed-forward 8-tap-decision
feedback digital equalizer for 16 Gb/s
I/Os," in Proc. European Solid State Circuits Conf., 2014, pp. 455-458.
[20] S. Kasturia and J. H. Winters, "Techniques
for high-speed implementation of nonlinear cancellation," IEEE J. Sel. Areas Commun., vol. 9, no. 5, pp. 711-717, 1991.
[21] K. Parhi, "Design of multigigabit multiplexer-loop-based decision feedback
equalizers," IEEE Trans. Very Large Scale
Integr. (VLSI) Syst, vol. 13, no. 4, pp. 489-
493, Apr. 2005.
[22] S. Kiran, S. Cai, Y. Luo, S. Hoyos, and S.
Palermo, "A 32 Gb/s ADC-based PAM-4
receiver with 2-bit/stage SAR ADC and
partially-unrolled DFE," in Proc. 2018 IEEE
Custom Integrated Circuits Conf., pp. 1-4.

About the Authors
Samuel Palermo (spalermo@tamu
.edu) received his B.S. and M.S. degrees in electrical engineering from
Texas A&M University in 1997 and
1999, respectively, and his Ph.D. degree in electrical engineering from
Stanford Universit y in 2007. He
worked previously with Texas Instruments and Intel. He is currently an
associate professor in the Electrical
and Computer Engineering Department of Texas A&M University. His research interests include high-speed
electrical and optical interconnects,

high-performance clocking circuits,
and sensor systems.
Sebastian Hoyos (hoyos@tamu
.edu) received his B.S. degree from
the Pontificia Universidad Javeriana
in 2000 and his M.S. and Ph.D. degrees from the University of Delaware in 2002 and 2004, respectively,
all in electrical engineering. He was
a postdoctoral researcher with the
Berkeley Wireless Research Center.
He is currently an associate professor
in the Electrical and Computer Engineering Department of Texas A&M
University. His research interests
include telecommunication systems,
digital signal processing, and analog
and mixed-signal circuit design.
Shengchang Cai (shengchangcai@
tamu.edu) received his B.S. degree
in microelectronics from Fudan University in 2012 and his Ph.D. degree
in electrical engineering from Texas
A&M University in 2018. In 2015, he
was a SerDes architect intern with Freescale. His research interests include
high-speed analog-to-digital converters, high-speed electrical links, and
radio-frequency photonics.
Shiva Kiran (luminoss1@tamu
.edu) received his B.E degree in telecommunication engineering from
Bangalore Institute of Technology and
his M.Tech. degree in microelectronics
and very large-scale integration design
from the Indian Institute of Technology, Kharagpur. He is currently working toward a Ph.D. degree at Texas
A&M University, College Station. His
research interests include system and
circuit design for high-speed input/
output and statistical modeling techniques for high-speed link systems.
Yuanming Zhu (zymk1989@tamu
.edu) received his B.S. degree in electronic science and technology from
Wuhan University of Technology and
his M.S. degree in integrated circuit
engineering from the University of
Chinese Academy of Sciences. He is
currently working toward a Ph.D. degree at Texas A&M University, College
Station. His research interests include
high-speed analog-to-digital converters and high-speed electrical links.

IEEE SOLID-STATE CIRCUITS MAGAZINE

su m m E r 2 0 18

47
IEEE Solid-States Circuits Magazine - Summer 2018

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Summer 2018
