IEEE Solid-States Circuits Magazine - Summer 2018 - 62

The beauty of this technique is that it
works for any input that is not correlated
with the chopping signal.
sampling rate fS /M. Gain mismatches
between the parallel channels cause
amplitude modulation of the input
samples by the sequence of channel
gains. In the frequency domain, this
mismatch causes scaled copies of the
input signal spectrum to appear centered around integer multiples of the
channel sampling rate. Ideally, each
channel should sample T seconds
after the previous channel, where
T = 1/fS and fS is the overall sampling rate. Deviations from the ideal
sampling instants can be represented
as a sequence of sample-time errors
that phase modulate the input Vin. In
the frequency domain, this modulation produces undesired components
at the same frequencies as the errors
from gain mismatch. However, the

magnitudes of these components are
now proportional to the input frequency because they are proportional to
the slope of the input. Background
calibration techniques that overcome
these errors are described next.

Random Chopper-Based
Background Offset Calibration
Figure 2 shows a block diagram of
a random chopper-based offset calibration for one channel in a time-interleaved ADC [6]. A related technique
was independently developed [7]. The
notch filter at the output digitally removes the offset from the sampleand-hold amplifier (SHA) and the ADC
in a channel [8]. However, if the analog input is connected directly to the
SHA, bypassing the multiplier (chop-

ADC1
ADC2

Dout(nT)

Vin(t )

fS = 1/T

fS
ADCM

Analog
Demux

Digital
Mux

Background Gain Calibration

fS /M
Figure 1: A block diagram of a time-interleaved ADC.

Notch Filter

Chopping SHA
Analog
Input

C [n ]

SHA1

ADC1

S1
+

−

Y1
µ

×
C [n ]

V1
Accum

Figure 2: A block diagram of the random chopper-based offset calibration for one channel
in a time-interleaved ADC.

su m m e r 2 0 18

IEEE SOLID-STATE CIRCUITS MAGAZINE

per) shown in the chopping SHA,
notches in the input spectrum are introduced at integer multiples of the
channel sample rate. To avoid introducing these notches, two choppers
are used, one in the analog domain at
the input and the other in the digital
domain at the output. These choppers multiply by a pseudorandom
binary signal C [n], where n is a
time index. C [n] = !1 and has zero
mean. Also, it is uncorrelated with
the analog input. The input chopper
spreads the input over all frequencies. Then the notch filter removes
the dc component, which stems
mainly from offsets in the SHA and the
ADC. Finally, the output chopper shifts
the input signal back to the frequencies where it started. The part of the
output that comes from the input
is not affected much by this process
for two reasons. First, it is chopped
twice, and C 2 [n] = 1. Second, a tiny
value of n is used in practice to limit
the steady-state variation at the notchfilter output to a negligible level. With
a tiny value of n, the bandwidth of the
notch filter is very small. This technique is applied to each channel in
the time-interleaved array to overcome the effect of offset mismatch.
The beauty of this technique is that
it works for any input that is not correlated with the chopping signal. This
technique has been used in commercial practice [9], [10].

Figure 3 shows a block diagram of the
gain calibration for one channel in a
time-interleaved ADC [8]. The randomnumber generator (RNG) produces
a dither signal equal to ! 1 with zero
mean and uncorrelated with the input.
The dither is converted to the analog domain by a 1-bit DAC, added to
the input, and digitized along with the
input by the ADC. The ADC output is
multiplied by G, which is the output
of an accumulator. Then the dither is
subtracted from the multiplier output,
producing D out, which is the calibrated output of the channel. The accumulator operates in a negative feedback
loop and finds G to eliminate the

IEEE Solid-States Circuits Magazine - Summer 2018

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