IEEE Solid-States Circuits Magazine - Summer 2018 - 65

the difference between the front- and
back-end outputs. Also, it foreground
calibrates offset mismatches in the interleaved array. A third example uses
a folding flash ADC with two interleaved channels in the front end to reduce the required power dissipation at
high conversion rates and to increase
the maximum conversion rate [16].
Also, offset and timing errors are both
background calibrated in this project.
Offset errors are handled as in [14].
However, the timing calibration used
in [15] is not adequate here because
the front end also needs timing calibration since it is time interleaved too.
The timing calibration is done in the
background by using an extra cycle in
each channel to compare the timing of
its sample clock to that of a reference
clock and then making corrections in
the analog domain.

Slice-Order Shuffling
In a conventional time-interleaved
ADC, M channels are used to increase
the conversion rate by a factor of M.
If each channel operates at its maximum conversion rate, only one channel is ready to sample and digitize
a new input when the time to begin
processing that input arrives. In this
case, the channels are always selected in the same order. Therefore,
if the ADC input is periodic, the offset, gain, and timing errors stemming
from interleaving are periodic too. As
a result, the errors appear at certain
discrete output frequencies with a
periodic input. This concentration of
errors can limit the spurious-free dynamic range (SFDR), which is important in communication applications,
where interleaving artifacts from
these errors with a strong signal can
act as interference to the reception of
a weak signal.
One way to overcome this problem
is to increase the number of interleaved channels without increasing
the overall sampling and conversion
rate [17], [18]. With DM extra channels, DM + 1 channels are ready to
sample and process a new input each
time a new sampling instant arrives
[18]. If one of the available channels is

BG calibration has enabled great improvements
in the power and area efficiency of data
converters, but it has created new challenges too.
randomly selected to process the new
input, the interleaving artifacts arising
with a periodic input are no longer
periodic, spreading out the errors
in the frequency domain, and improving the SFDR. Also, extra channels are
potentially useful for allowing calibration to operate in the background [19]
and for yield enhancement.
Disadvantages of slice-order shuffling are that the extra channels increase both the loading on the input
buffer and the required die area. However, if each channel is a successiveapproximation-register ADC, its static
power dissipation can be negligibly
small, leading to little overhead in
power dissipation with this technique
except as follows. The input buffer
dissipates extra power to maintain the

φ1

same bandwidth with an increased
load. Also, the increase of loading on
shared dynamic signals such as clocks
increases the power dissipation. This
technique has been used in commercial practice [20], [21].

First- or Front-Rank SHA Instead
of Timing Calibration
Figure 8 shows a block diagram of a
time-interleaved ADC with an SHA in
front of the entire array. The input
SHA is called a first- or front-rank
SHA [22]. The main advantage of this
structure is that it reduces the jitter in the input samples because the
first-rank SHA samples all the inputs
to be digitized by this ADC. However, the main disadvantage is that
the first-rank SHA has high power

ADC1

φ2

ADC2

Vin (t )

Calib.
φM
φ
fS

Dout (nT)

ADCM

Flash
ADC

φ1
φM

Offset Corr.
Clock
Gen

Timing Corr.

Figure 7: A block diagram of a flash-assisted, time-interleaved ADC.

ADC1
SHA
Vin (t )

ADC2

Dout (nT)

Analog
Demux

ADCM
fS /M

fS = 1/T
Digital
Mux

Figure 8: A block diagram of a time-interleaved ADC with a first-rank SHA.

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IEEE Solid-States Circuits Magazine - Summer 2018

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