IEEE Solid-States Circuits Magazine - Summer 2018 - 66

At first, calibration was done only in the analog
domain, but now it is done in the analog
domain, the digital domain, or both.
dissipation to operate as fast as all
the interleaved channels together.
This technique has been used recently in a very demanding application
instead of calibration to overcome
the effects of timing errors [10]. Since
this technique is not a type of calibration, the example in [10] shows that
calibration does not always offer the
best solution to overcome systematic
ADC errors.

Analog Calibration of Offset,
Gain, and Timing Errors

Vin

Digital Calibration of Offset,
Gain, and Timing Errors
Figure 9(b) shows a block diagram of
one channel in a time-interleaved array with digital calibration of offset,
gain, and timing errors. Digital calibration simplifies verification and
portability to new process nodes.
A l s o, it r e duce s t h e n u m b e r of
changes that are needed in sensitive
analog circuits to allow calibration,

Voff

Figure 9(a) shows a block diagram
of one channel in a time-interleaved
array with analog calibration of offset, gain, and timing errors. Analog
calibration has some important advantages, stemming in part from the
fact that the errors are corrected before quantization. For example, offset calibration in the analog domain
does not reduce dynamic range, unlike offset calibration in the digital
domain [19]. Also, extra bits are not
required in each channel to reduce
the error below 1 least significant
bit (LSB), simplifying the interface to
the calibration. In addition, the analog calibration of timing errors does
not increase the latency because an-

alog timing corrections can be made
without waiting to collect the outputs from all the channels. Also, the
analog calibration of timing errors
can work both above and below the
Nyquist bandwidth limit. However,
analog calibration increases design
and verification time and requires
analog calibration signals to settle,
which can make analog calibration
slow compared to digital calibration
(especially when power dissipation
is low). Also, it requires that analog
correction circuits are tightly integrated with sensitive analog circuits
in the data converters under calibration. Finally, moving analog calibration techniques established in one
process node to a new node is normally difficult.

Clock

DAC

∆t

Voff

−
Σ

Dout

ADC Channel

Vin

ADC Channel

Voff

∆t

−
Dig. Delay

Dout

(b)
Figure 9: A block diagram of one channel in a time-interleaved ADC with (a) analog calibration of offset, gain, and timing errors and (b) digital calibration of these errors.

su m m e r 2 0 18

IEEE SOLID-STATE CIRCUITS MAGAZINE

Summary of Offset, Gain,
and Timing Calibrations
Table 1 summarizes the type of offset, gain, and timing calibrations in
some time-interleaved ADCs. A trend
in changing from analog to digital calibration techniques does not appear. In
fact, the trend under timing calibration is in the opposite direction, starting with the use of a first-rank SHA
[22], then changing to analog [23], and
then digital calibration [6]. However,
most recently, analog calibration is being used again to eliminate the need
for complicated digital filters to make
small timing corrections [15], [16],
[26]. Similarly, a trend in changing
from foreground (FG) calibration to
background (BG) calibration does not
appear in Table 1. This observation is
surprising because BG calibration can
track variations during normal operation, unlike FG calibration. However,
FG calibration is simpler and less expensive than BG calibration. As a result, FG calibration is preferred to
overcome errors that are essentially
independent of temperature and power supply changes, such as capacitor
matching, for example. Also, FG calibration is often used with BG calibration to reduce the range over which
errors need to be tracked. Finally, FG
calibration can overcome the problems considered next.

Clock

(a)

and it can scale in advanced processes. However, digital calibration reduces dynamic range. Also, it increases
latency, which is a problem in communications applications in which data
converters operate in negative feedback loops because increasing the
delay inside a negative feedback loop
decreases its phase margin. Finally,
digital calibration for timing errors
limits the input bandwidth to one Nyquist zone.

Challenges Created by
Background Calibration
BG calibration has enabled great improvements in the power and area efficiency of data converters, but it has
created new challenges too, described
below. Challenges related to assumptions

IEEE Solid-States Circuits Magazine - Summer 2018

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