IEEE Solid-State Circuits Magazine - Winter 2018 - 10

Variance (Steps)2

80
60
40
20

Step Number

(a)

(b)

100

Average (Steps)
20

0
-20

-15
-20

120
100

Average and Variance

10
5
0
-5
-10

0
10
20
30
40
50
60
70
80
90
100

Distance (Steps)

Figure 5: (a) Ten simulated distances from the origin for ten walks, each consisting of a total
of 100 steps, and (b) the average and the variance of the ten distances as functions of the
step number.

σ∆T

∆T
Average Delay = ∆T
log σ∆T (∆T)
Slope = 1/2

κ √ ∆T

log ∆T

Figure 6: The standard deviation of the clock edge after N periods grows with the square
root of N. (The figure was slightly modified from [2].)

continue this random walk. This is
shown in Figure 5(a), where we have
simulated ten random walks (i.e., random walks taken by ten different individuals), including 100 steps in each
walk. The curve in each color represents the distance from origin for a
particular walk as a function of the
number of steps. Figure 5(b) plots the
average distance and the distance variance of the ten walks. It is clear that, at
any time, the average location of the
ten random walks hovers around zero,
independent of the number of steps

W i n t e r 2 0 18

taken. In fact, this average is expected
to approach zero as we increase the
number of random walks. On the
other hand, the spread of the random walks, as captured by the variance of the location, increases linearly
with the number of steps.
Let us now return to our ring oscillator and observe that the excess
delay caused by thermal noise is also
an i.i.d. process. In other words, the
excess delays of the inverters used in
the ring, as well as the excess delays
of the same inverter used in two dif-

IEEE SOLID-STATE CIRCUITS MAGAZINE

ferent instances, are independent of
each other, yet all have the same distributions. The excess delay, however,
is a slightly more complicated random
walk than the example we provided.
Excess delay not only shows randomness in its sign (taking positive and
negative values) but also shows randomness in step size (some steps may
be smaller than others). In this case,
every step can assume any real value
(not just binary values). Nevertheless,
the conclusion remains the same, i.e.,
the variance of excess delay increases
linearly with time.
If you wish to probe further, see a
highly cited paper published in 1997 by
John A. McNeill [2]. This paper shows,
with experimental results, that the standard deviation of a clock edge produced
by an N-stage ring oscillator increases
with the square root of time, or, equivalently, the variance of the deviation
grows linearly with time. Figure 6 captures this idea. This paper also shows
how this variance is curtailed, i.e., will
not grow beyond a limit, once we put
the ring oscillator inside a control loop.
The uncertainty in time or deviation from the nominal time is called
jitter. For an in-depth treatment of
jitter, see [3] and [4].
In summary, we have described
intuitively how the period of oscillation in a ring oscillator is a random
signal and how it will result in a deviation in the clock edge (say its rising
edge), from its nominal position,
that grows with the root of number
of periods. We have explained how
this phenomenon can be explained
by a random walk process.

References

[1] A. Papoulis and S. U. Pillai, Probability,
Random Variables and Stochastic Processes, 4th ed. New York: McGraw-Hill, 2002.
[2] J. A. McNeill, "Jitter in ring oscillators,"
IEEE J. Solid-State Circuits, vol. 32, no. 6,
pp. 870-879, June 1997.
[3] N. Da Dalt (2012, Feb.) Jitter: Basic and advanced concepts, statistics, and applications. Proc. ISSCC. [Online]. Available: http://
sscs.ieee.org/education/tutorials-on-line
[4] N. Da Dalt and A. Sheikholeslami, Understanding Jitter and Phase Noise -A System
Perspective. Cambridge, U.K.: Cambridge
Univ. Press, 2018.

http://sscs.ieee.org/education/tutorials-on-line http://sscs.ieee.org/education/tutorials-on-line

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018