IEEE Solid-State Circuits Magazine - Winter 2018 - 34

on the thermal-noise-limited efficiency using a combination of SAR
and noise shaping.
Figure 7 shows achieved bandwidth as a function of SNDR. Sampling
jitter or aperture errors coupled with
an increased noise bandwidth make
achieving both high resolution and
high bandwidth a particularly difficult task. While, ten years ago, a stateof-the-art data converter showed
an aperture error of approximately
1ps rms, in recent years, designs with
aperture errors below 100 fs rms have
been published at a wide range of
resolutions. ISSCC 2018 further advances the art with the first data
converter having an input frequency
above 30 GHz, using a 64-times timeinterleaved SAR ADC.

Communication Systems:
Radio Frequency
Subcommittee Chair: Piet
Wambacq, IMEC, Leuven, Belgium
This year, ISSCC 2018 features ongoing advances in radio-frequency (RF)
building blocks for broadband communications, millimeter-wave (mmwave) sensing, and terahertz imaging.
Topics include frequency generation;
efficient transmit and robust receive
techniques for emerging cellular narrowband IoE applications; full-duplex,

fifth-generation (5G) massive multipleinput, multiple-output (MIMO); and
backhaul link systems as well as realtime near-field imaging. Papers showcase advances in voltage-controlled
oscillators (VCOs) and wideband mmwave local-oscillator (LO)-generation
blocks for 5G networks as well as in
digitally intensive frequency synthesizers for communication and chirpbased radar-sensing applications.

Frequency Generation and Synthesis
In the area of VCOs, the trend is toward
achieving low phase noise with architectural advances such as waveformshaping LC tanks or multicore and
multiple-resonator-based circuits. As
illustrated in Figure 8, the phase noise
of oscillators tends to increase at higher carrier frequencies. Achieving lower
phase noise requires novel circuit
topologies or spending more power.
ISSCC 2018 presents a low-voltage inverse class-F VCO with a 196.2-dBc/Hz
FOM and a 15-GHz BJT/CMOS (BiCMOS)
VCO exhibiting −124-dBc/Hz phase
noise at -MHz offset.
Wideband mm-wave LO-generation building blocks become essential
for next-generation broadband communications systems. At ISSCC 2018,
injection-locked frequency-multiplierbased techniques are demonstrated
to support multiple bands in the

1.E+11

-80.0
Phase Noise (dBc/Hz)

1.E+10
fin,hf (Hz)

1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03

10 20 30 40 50 60 70 80 90 100 110 120
SNDR at fin,hf (dB)

ISSCC 1997-2008
Jitter = 1 psrms
ISSCC 2009-2017
ISSCC 2018

VLSI 1997-2008
Jitter = 0.1 psrms
VLSI 2009-2017

Figure 7: Bandwidth versus SNDR.

mm-wave region. At subterahertz frequencies, stable sources are critical
for imaging systems. ISSCC 2018 will
present a BiCMOS 300-GHz oscillator
with a very stable frequency output
with no need for a phase-lock loop
(PLL) or an off-chip crystal. The oscillator provides a peak output power of
−13.9 dBm from 302 to 332 GHz.
In the field of frequency synthesizers, ISSCC 2018 will highlight advances
in digital architectures enabling compact-area, low-power, low-noise implementations. A 653-μW fractional-N
all-digital PLL for IoE applications will
be presented. By leveraging an isolated constant-slope digital-to-time converter (DTC), it achieves an integrated
jitter of 0.53 ps at 2.44-GHz output
with a power consumption of 0.98 mW,
corresponding to an FOM of −246 dB.
Another development presented is a
frequency synthesizer comprising an
all-digital frequency-locked loop and a
type-I PLL with an LC VCO occupying
only 0.01 mm2 in 65-nm CMOS, achieving a −254-dB jitter FOM from 4.6 to
5.6-GHz output.
An important trend is a rising interest in frequency synthesizers for
fully integrated chirp-modulationbased radar systems. At ISSCC 2018,
two papers will address this topic: one
shows a 23-GHz digital bang-bang PLL
for fast triangular and sawtooth chirp

W I n t E r 2 0 18

IEEE SOLID-STATE CIRCUITS MAGAZINE

-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0

100

1,000

Frequency (GHz)
2000-2017
ISSCC 2018
Trend Line

Figure 8: LC oscillator phase noise at 1-MHz offset versus carrier
frequency.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018