IEEE Solid-State Circuits Magazine - Winter 2018 - 37

Power Efficiency (mW/Gb/s)

1,000

150

140

130

120

110

100

Data Rate (Gb/s)

100

Process Node (nm)
2008
2012
2016

2009
2013
2017

2010
2014
2018

Figure 14 shows that the data rates
for published transceivers have kept
pace with these standards, enabled, in
part, by process-technology scaling.
However, continuing this remarkable
I/O scaling trend will be thwarted by
future difficulties in transistor scaling.
Significant advances in both energy
efficiency and signal integrity must be
achieved to enable the next generation
of low-power, high-performance computing systems. Papers at ISSCC 2018
include demonstrations of 112-Gb/s
pulse-amplitude modulation with
four-amplitude-level (PAM-4) transmitters in 10-nm and 14-nm CMOS as
well as a power-efficient 56-Gb/s ADCbased transceiver in 16-nm CMOS.

Energy Efficiency
and Interconnect Density
The power consumption of I/O circuits is a first-order design constraint
for systems ranging from cell phones
to servers. As the pin count and perpin data rate for I/O have increased,
so has the percentage of total power
consumed by I/O. Technology scaling
has enabled increased clock and
data rates and offers improved energy
efficiency, especially for digital components. However, simply increasing
per-pin baseband data rates with existing circuit architectures and channels
is not always a viable path, given fixed

ISSCC 2018

100

/30

0.1

2011
2015

Figure 14: Data rate versus process node and year.

Other

10×

Channel Loss at Nyquist (dB)

Figure 15: Transceiver power efficiency versus channel loss.

system-power limits. Figure 15 plots
the energy efficiency (expressed in
mW/Gb/s, which is equivalent to pJ/b)
as a function of channel loss for recently
reported transceivers. Looking at the
most aggressive designs, the data
indicate that the scaling factor between
link power and signaling loss is slightly
less than unity-and, in particular, that
a 30-dB channel loss corresponds to a
roughly ten times increase in pJ/b. Many
recent advances have reduced power for
high-speed link components through
circuit innovation: these include lowpower receiver equalization [decision
feedback equalization (DFE) and continuous-time linear equalization (CTLE)],
CMOS resonant clocking, low-swing
voltage-mode transmission, and links
with low-latency power-saving states. At
ISSCC 2018, a 112-Gb/s PAM-4 transmitter in 10-nm CMOS that consumes only
1.16 pJ/b will be demonstrated. Also
presented will be an 8-b DAC-based
112-Gb/s PAM-4 transmitter with a power
efficiency of 2.55 pJ/b.

Electrical Interconnect
There has been increasing demand
for very-high-data-rate communication
across a wide variety of channels. Some
types of channels, especially those
related to medium-distance electrical
I/O (such as server backplanes), must
support high data rates over high-loss

channels. For these links, the key
to scaling has been improvements in
equalization and clock/data recovery.
Recent high-speed transceivers use a
combination of fully adaptive equalization methods, including transmit finiteimpulse response (FIR), receive CTLE,
and DFE, as well as receive FIR and/
or infinite-impulse response FIR filter
efficiency. As a result, recent receivers
achieve data rates above 28 Gb/s across
channels with up to 50 dB of loss.
ISSCC 2018 will present examples
of transceivers that are starting to
extend the equalization range of
56-Gb/s wireline communication. One
paper describes a 28.05-Gb/s multistandard transceiver that compensates
40-dB loss with an energy efficiency
of 6 pJ/b. Another paper presents a
fully adaptive 19-56-Gb/s transceiver
with a 3-7-b reconfigurable ADC that
achieves power efficiency of 6.4 pJ/b
over a 7.4-dB channel.

Optical Interconnect
As the demand for higher bandwidth has accelerated and electrical
channel impairments have become
increasingly severe with rising perlane data rates, optical interconnects
have become an increasingly attractive
alternative to traditional electrical wireline interconnects. Optical communication has clear benefits for high-speed,

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