IEEE Solid-State Circuits Magazine - Winter 2018 - 39

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Figure 19: On-die cache-size trends. (The red diamond designates
an MCM.)

Figure 18: Chip-complexity scaling trends. (The red diamond
designates an MCM.)

dreds of TOPS/W for a mixed-signal
implementation. Several papers at
ISSCC 2018 treat the energy efficiency
of fully connected network acceleration. In such networks, the bottleneck is the memory load/stores, and,
as such, innovative solutions include
the fabrication of a three-dimensional
(3-D) stack of processing and memory
dies, as well as smart memory interfaces enhancing data reuse. These innovations clearly bring DNNs within
reach of battery-operated devices.
Figure 23 illustrates deep-learning
processor efficiency and throughput

improvements for DNNs and CNNs
presented at ISSCC 2018, as compared to the state of the art in 2017.

Digital Systems: Digital Circuits
Subcommittee Chair: Edith Beigne,
CEA-LETI, Grenoble, France
The demand for higher performance
across ubiquitously connected energyconstrained platforms ranging from
the IoE to cloud data centers continues to drive innovations in all CMOS
digital-circuit building blocks, with
goals of improving energy-efficient

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every five years (Figure 22). Changes
are modest this year relative to last
year; however, the IEEE 802.11ax
standard is on the near horizon. Both
mm-wave and massive MIMO technologies are being actively studied to realize 5G communication. The explosion
of IoE devices will require the evolution
of narrowband wide-area networks.
Deep learning is a rapidly evolving topic at ISSCC 2018. The computational complexity of typical deep
neural networks (DNNs) impedes
their execution on resource-scarce
mobile or wearable devices. Last
year, several innovative solutions
were introduced to enhance throughput and improve energy efficiency,
mostly focusing on the efficiency
of convolutional neural networks
(CNNs). The current state of the art
still faces two significant challenges:
1) a need to improve energy efficiency for ultralow-power applications
and 2) solutions for efficient execution of fully connected nonconvolutional networks.
To realize improved energy efficiency, there is a trend toward
reduced-precision networks, with binary networks as the extreme case
(recently, the first binary neuralnetwork accelerator appeared). This
year, ISSCC 2018 pushes peak efficiency from several tens of trillions
of operations per second (TOPS)/W
(digital accelerators) to beyond hun-

20

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Figure 20: Clock-frequency trends for mobile CPUs.

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I n t E r 2 0 18

39



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018

Contents
IEEE Solid-State Circuits Magazine - Winter 2018 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2018 - Cover2
IEEE Solid-State Circuits Magazine - Winter 2018 - Contents
IEEE Solid-State Circuits Magazine - Winter 2018 - 2
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