IEEE Solid-State Circuits Magazine - Winter 2018 - 43

Innovative Topics: Imagers
Subcommittee Chair: Makoto Ikeda,
University of Tokyo, Japan
CMOS image sensors remain one of
the fastest-growing segments of the
semiconductor industry, with double-digit compound annual growth
rates. Image sensors are required

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32 28 22 20 16
Technology Node (nm)

Figure 27: Bit-cell and VMIN scaling trends for SRAM.

nAnD Flash Memory

1,000
Data Bandwidth (GB/s)

NAND Flash memory continues to advance toward higher density and lower
power, resulting in low-cost storage
solutions that are replacing traditional hard-disk storage with solid-state
disks. In mass-production semiconductor industries, 3-D memory technology
has been the mainstream for NAND
Flash memory. At ISSCC 2018, both a
1-Tb 4-b/cell that achieves 5.63-mm2/
Gb areal density and a 512-Gb 3-b/cell
3-D NAND with 96 stacked word-line
layers will be presented, continuing
the trend toward satisfying the evergrowing demand for increased density
requirements and lower manufacturing
costs. Recent NAND developments at
ISSCC 2018 show not only higher density but also higher performance (over
57-MB/s program throughput and
1.0-GB/s read throughput), all at lower
voltages (1.8-1.2 V). Figure 31 shows
the observed trend in NAND Flash capacities at ISSCC over the past 15 years.

0.999

1.000

Bit Size (µm2)

Over the past decade, significant investment has been made in the emerging
memories field to find an alternative to
floating-gate-based nonvolatile memory (NVM). The emerging NVMs, such
as phase-change memory (PRAM),
ferroelectric RAM (FeRAM), STT magnetic RAM (STT-MRAM), and RRAM, are
showing potential for achieving high
cycling capability and lower power per
bit in read/write operations. Figure 29
highlights 3-b/cell (TLC) NAND Flash
and 4-b/cell (QLC) NAND Flash write
throughput. Figure 30 shows a significant increase in NAND Flash capacity
from 768 Gb to 1 Tb at ISSCC 2018.
Such high areal densities are achieved
through advances in 3-D vertical bit/
cell-stacking technologies.

VMIN (V)

nonvolatile Memories

)

HBM(x
100

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GDDR

WIO2

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LPDD

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DDR3
DDR4
GDDR4
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LPDDR3
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LPDDR4X
LPDDR5
WIO
HBM

Figure 28: DRAM data-bandwidth trends. WIO: wide I/O.

components in most mobile devices,
which now include multiple frontand rear-facing cameras. The other
applications that continue to drive
t h e de m a n d fo r i m a ge s e n s o r s
include autonomous driving, smart
security, wearables, gaming, VR, AR,
the IoE, and biomedicine.
Because they enable increasing onchip functionality without detracting from image quality, 3-D stacked
image sensors have become more
popular. At ISSCC 2018, six out of
the ten papers on image sensors use
a 3-D stacking process to preserve
most of the top-layer area for light
sensing, while keeping the readout
and image-signal-processing circuits
on the bottom layer. In one paper, a
14-b ADC is stacked under each pixel

using a copper-copper hybrid bonding technology.
As seen at previous ISSCCs, the race
to higher resolution and smaller pixels
has slowed slightly but never stopped.
At ISSCC 2018, a 0.9-μm pixel with a
full-depth deep-trench isolation that
reaches a performance level exceeding
the current-generation 1.0-μm pixel in
both the saturation level and readout
noise will be presented. The broadcasting industry continues to push
the array size toward, and beyond,
the 8-k/4-k or 33-Mpixel resolution,
with frame rates exceeding 120 f/s. At
ISSCC 2018, a 33-Mpixel, 480 f/s CMOS
image sensor will be presented.
We observe continued development
of depth sensors, using either direct
or indirect time-of-flight technology,

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018