IEEE Solid-State Circuits Magazine - Winter 2018 - 8
C ircu it Intu itions
Ali Sheikholeslami
Random Walk in a Ring
W
Welcome to the 16th article in the
"Circuit Intuitions" column series.
As the title suggests, each article
provides insights and intuitions into
circuit design and analysis. These
articles are aimed at undergraduate
students but may serve the interests of other readers as well. I would
appreciate your comments and feedback on this article as well as your
requests and suggestions for future
articles in this series. Please e-mail
me at ali@ece.utoronto.ca.
Among the many concepts that a
circuit designer should be familiar
with is the concept of random process and, in particular, the concept of
a random walk process. This article
introduces these concepts in the context of a ring oscillator and its period
of oscillation.
Consider three inverters in a ring,
as shown in Figure 1. A quick inspection of this circuit reveals that the
output of this circuit (say v 3 ) cannot
stay at digital 0 or 1 for too long. If it
is 0 at an instant, it will force v 1 and
v 2 to 1 and 0, respectively, and this
in turn will force v 3 to flip to 1. Similarly, this 1 will only last for three inverter delays before it changes back
to 0. As a result, the circuit oscillates
and produces a periodic clock waveform with a period of oscillation
being 6t pd, where t pd is the propagation delay of an ideal inverter. Note
that, in general, the inverter delay
for a rising input transition (often denoted by t phl) may be different than
Digital Object Identifier 10.1109/MSSC.2017.2771101
Date of publication: 31 January 2018
8
W i n t e r 2 0 18
1
T = 6 tpd
v1
2
v2
3
v3
tpd tpd tpd
Figure 1: A three-stage ring oscillator and its corresponding ideal waveforms.
VDD
VDD
l2(t )
ln2(t )
C
M2
vin
vo
vo
(b)
vo
M1
C
C
l1(t )
(a)
ln1(t )
(c)
Figure 2: (a) A CMOS inverter, (b) an equivalent model when the input voltage steps down
from VDD to zero, and (c) an equivalent model when the input voltage steps up from zero to VDD .
the corresponding delay for a falling
input transition (often denoted by
t plh), but for simplicity, we have assumed t phl = t plh = t pd.
What we just described is what
most of us have seen in an introductory course on digital electronics. Let
IEEE SOLID-STATE CIRCUITS MAGAZINE
us now consider the fact that t pd is not
constant but rather a random variable
due to the thermal noise of the transistors forming the inverter.
Figure 2(a) shows a schematic of a
complementary metal-oxide-semiconductor (CMOS) inverter, consisting
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018
Contents
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IEEE Solid-State Circuits Magazine - Winter 2018 - Contents
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