IEEE Solid-States Circuits Magazine - Spring 2019 - 13

Rop

M1

VF

Vout

CG

RF

VDD
M2

RL(R1 + R2)

D1

FIGURE 13: The open-loop follower-based
LDO including capacitances.

With rO1 1 3, we employ the model
shown in Figure 12(b), assuming
(R 1 + R 2) < R L is large enough, to obtain

1
. c 1 + R1 m
.
R 2 g m1rO1 A 1

(14)
(15)

Compared to (5), the follower-based
LDO has a factor of g m1rO1 advantage
in PSRR. The output noise of this
LDO is found as illustrated in Figure 7
for the previous topology:
2
V2
V 2n, out = c 1 + R 1 m e V 2nA + n2M o .
R2
A1

Vout

CM

R2
A
R2 + R1 1

Vout
R out
=
R out + rO1
Vin

Lin

RF

(16)

Thus, the two structures have the same
output noise.
The prior calculations predict that
the PSRR, output impedance, and
output noise of the follower-based
LDO exhibit the same general frequency-domain behavior as those
of the current-source-based topology. However, the source follower
leads to different results. Drawing
the open-loop LDO as in Figure 13,
we recognize that the output pole is
roughly equal to 1/(g -m11C M ), which
assumes a much higher value than
that in Figure 10. Moreover, because
of the source follower's bootstrapping of C G, the op amp does not see
this entire capacitance. For example, if the gain from VF to Vout is
0.7, we can apply the Miller theorem to C G, concluding that about
30% of this capacitance loads the op

Iin
M1

FIGURE 14: The TIA using an inverter.

amp. Thus, the follower-based LDO
generally provides a greater compensated bandwidth than does the
current-source-based topology. In
both LDO structures, we first select
the smoothing capacitor to obtain
the desired load regulation at a given
frequency (e.g., at the switching frequency of the divider in Figure 2) and
then compensate the loop by adjusting the op amp's dominant pole.

Cp

Answers to Last Issue's Questions
1) Calculate the input-referred noise
current of the transimpedance
amplifier (TIA) shown in Figure 14.
Does this noise increase or decrease if we consider channellength modulation?
Let us assume m = 0. We first
compute the circuit's transimpedance to be 1/(g m1 + g m2) - R F . -R F .
Next, we find the output noise voltage
resulting from R F and the two transistors as 4kTR F + 4kTc/ (g m1 + g m2).
Dividing the latter by R 2F gives the
input-referred noise current:
I 2n, in =

Vout

FIGURE 15: The TIA with series peaking.

In the presence of channel-length
modulation, the gain and the output
noise voltage drop by the same factor. Thus, the input-referred noise
current does not change.
2) How should L in be chosen in Figure 15 so that we have ~ -3dB .
[ 2 (1 + A 0)]R F C p ? For this second-order system, we select a
damping factor g = 2 /2, which
leads to

Questions for the Reader
1) How does C M shape the PSRR of
the circuit in Figure 9?
2) The op amp gain in Figure 12(a) falls
at high frequencies. Can we place a
capacitor in parallel with R 1 to counteract this effect and maintain a relatively constant loop gain?

-
A0
+

L in = R F .
Cp
A 0 +1

(18)

References

[1] L. C. Delatorre, "Battery low voltage cutoff
and regulator," U.S. Patent 3445746, May 20,
1969.
[2] K. D. Jenkins, "Low drop voltage regulator," U.S. Patent 2519377, Aug. 22, 1950.
[3] J. M. Moreau, "Regulator with a low dropout voltage," U.S. Patent 4543522, Sept. 24,
1985.
[4] G. A. Rincon-Mora and P. E. Allen, "Optimized frequency-shaping circuit topologies for LDOs," IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process.,
vol. 45, no. 6, pp. 703-708, 1998. doi:
10.1109/82.686689.
[5] H. J. Shin, S. K. Reynolds, K. R. Wrenner, T.
Rajeevakumar, S. Gowda, and D. J. Pearson,
"Low-dropout on-chip voltage regulator
for low-power circuits," in Proc. 1994 IEEE
Symp. Low Power Electronics, pp. 76-77.
[6] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, "Full on-chip CMOS lowdropout voltage regulator," IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 54, no. 9,
pp. 1879-1890, 2007. doi: 10.1109/TCSI.2007
.902615.
[7] M. Al-Shyoukh, H. Lee, and R. Perez, "A
transient-enhanced low-quiescent current
low-dropout regulator with buffer impedance attenuation," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, 2007.
doi: 10.1109/JSSC.2007.900281.

4kTR F +4kTc/(g m1 +g m2)
. (17)
R 2F

IEEE SOLID-STATE CIRCUITS MAGAZINE

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IEEE Solid-States Circuits Magazine - Spring 2019

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