IEEE Solid-States Circuits Magazine - Spring 2019 - 28

the component, as shown in the figure. Using the traditional dog-bone
layout approach, it is possible to separate the majority of the vertical transitions while introducing power and
ground signal return vias between
the signal vias for dramatically improved SI. Figure 24 compares the
field strength/coupling between balls
in the GDDR6 ball grid [Figure 15(a)
and (b)] with a fictitious checkerboard
solution [Figure 15(c)] and reports
a significant coupling reduction,
translating into a 15.8-dB decrease in
crosstalk at the worst-case ball location. This experiment suggests that
coupling between vias (which are significantly taller and therefore more
sensitive than the package balls) may
be mitigated through thoughtful via

VDD

VSS

DQ

VSS

VPP

VSS

DQ

DQ

DQ

VDDQ

VDDQ EDC

VSS VDDQ

VSS

VSS

DBI

VSS

WCK

WCK

VDDQ

DQ

DQ

VSS

VDD

VSS

DQ

VSS VDDQ

VSS

DQ

VSS

CA2

NC

VDDQ VDD

CA0

VSS

CA4

CA9

CA8

CABI

RES

VDDQ

layout, including generous introduction of signal return vias.
As the PCB vias below the DRAM
were identified as one of the most
sensitive knobs in the channel performance, it is understandable that
steps to minimize the via impact are
an effective component of GDDR6
enablement (high-speed single-ended).
As suggested in Figure 18, back-drilling of the tall vias in the main PCB
is another key to increasing signaling margins. Removal of the via stubs
impacts both ISI (by eliminating a
major source of signal reflections)
and crosstalk (by doing away with the
crosstalk associated with the stubreflected signaling energy). The simulated 16-Gb/s data eyes presented
in Figure 25 provide a compelling

case for via back-drilling and, at the
same time, highlight the potentially
additive benefits of combining backdrilling with the GDDR6 one-tap DFE.
The additive nature of these distinct
forms of compensation can be understood by observing that they operate (to a degree) on different aspects
of the channel pulse response, as
observed in Figure 19. In addition,
via back-drilling addresses crosstalk, which the DFE does not explicitly do.
As speed increases, so does the
first postcursor of the channel pulse
response, thus increasing the effectiveness of the one-tap DFE. At the
same time, increases in speed drive
more signal energy across the resonance formed by the through-hole

Worst-Case
Coupling Improved
by 15.8 dB
dB (H Field)
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20

TMS

(a)

(b)

(c)

Volts

FIGURE 24: A coupling simulation example beginning from (a) the JEDEC-defined GDDR6 package ball-out (b) to the simulated fields between
GDDR6 package balls (c) to the fields between balls for a fictitious checkerboard solution.

Picoseconds
(a)

Picoseconds
(b)

Picoseconds
(c)

FIGURE 25: Peak-distortion-based data eyes corresponding to the worst-case data lines in an exemplary GDDR6 system channel: (a) baseline
(no back-drilling, no DFE), (b) back-drilled (no DFE), and (c) back-drilled plus one-tap DFE.

28

S P R I N G 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE
IEEE Solid-States Circuits Magazine - Spring 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2019
