IEEE Solid-States Circuits Magazine - Spring 2019 - 30

[26] S. J. Bae et al., "A 60nm 6Gb/s/pin GDDR5
graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques,"
in Proc. IEEE Int. Solid-State Circuits Conf.
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[27] H. Y. Joo et al., "A 20nm 9Gb/s/pin 8Gb
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[29] Graphics Double Data Rate (GDDR5)
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[30] Graphics Double Data Rate (GDDR5X)
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About the Authors
Timothy M. Hollis (thollis@micron
.com) received his B.S. degree in electrical engineering from the University
of Utah, Salt Lake City, in 2003 and
his Ph.D. degree in electrical engineering from Brigham Young University, Provo, Utah, in 2007, focusing
on channel equalization and jitter
attenuation circuits for high-speed
serial interconnects. He is currently a
Distinguished Member of the technical staff at Micron Technology Inc.,
Boise, Idaho, and serves as the technical lead for Micron's Signal Integrity
R&D team, with a focus on interface
pathfinding. He holds 138 issued U.S.
and international patents in the areas
of signal and power integrity, circuits,
and encoding. He serves as the technology chair of IEEE Solid-State Circuits
Magazine and is a Senior Member of
the IEEE.
Eric Stave received his B.S. degree
in electrical engineering from San
Diego State University, California, in
1989 and is now a Distinguished Member of the technical staff at Micron
Technology Inc., Boise, Idaho. He
started working at Micron in 1989 as
a Military Test Department engineer,
responsible for the static randomaccess memory (SRAM), dynamic RAM
(DRAM), and video RAM programs. He
then moved to the SRAM Department,
first working as a product engineer,
then as a characterization engineer,

S P R I N G 2 0 19

and finally as a design engineer. After his
SRAM work, he moved to DRAM product engineering, where he has focused
on input/output characterization
for double-data-rate 2 (DDR2), DDR3,
DDR4, low-power DDR3 (LPDDR3),
LPDDR4, and Hybrid Memory Cube
devices. He now works on DDR5
receiver/transmitter validation methodologies along with jitter measurement techniques. He holds 20 U.S.
patents and is an IEEE Senior Member.
Dave Ovard received his B.S. degree in electrical engineering from
the University of Utah, Salt Lake City,
in 1987. He has been a member of the
Signal Integrity R&D Group at Micron
Technology Inc., Boise, Idaho, since
1999. Prior to joining Micron, he
worked at Unisys, developing military
spread-spectrum data links; Omnipoint Communications, creating early
code-division multiple-access cellular
phone technology; and Micron Communications, engineering radio-frequency identification technology. He
holds more than 70 patents and is a
Member of the IEEE.
Roy Greeff received his B.S degree
in electrical engineering from the
University of Utah, Salt Lake City, in
1979. He is a senior member of the
technical staff at Micron Technology
Inc., Boise, Idaho, and has worked at
Micron for the last 20 years, first
with Micron Communications as a
radio-frequency engineer, then later
as a signal integrity engineer. Before
Micron, he worked in the defense
industry as a radio-frequency/microwave engineer. He holds more than
40 patents in the areas of communications and signal integrity.
Wolfgang Spirkl received his Ph.D.
degree in physics in 1990 from the Ludwig Maximilian University, Munich,
Germany, where he also completed
his habilitation degree in the field of
the thermodynamics of solar energy
conversion in 1998. From 1998 on,
he worked on the verification of embedded as well as discrete dynamic random-access memory. Currently, he is a
fellow at Micron Technology Inc., Boise,

IEEE SOLID-STATE CIRCUITS MAGAZINE

Idaho, working in the production and
testing of graphics double-data-rate
memories. He is a member of the ISSCC
memory subcommittee.
Martin Brox received his Diplom
and Ph.D. degrees from the University of Münster, Germany, in 1988
and 1992, respectively. In 1988, he
joined Siemens Corporate Research
and in 1992 moved to the IBM/Siemens/Toshiba dynamic randomaccess memory development project
in Burlington, Vermont. In 1997, he
returned to Siemens Munich, which
later became Infineon and Qimonda,
responsible for RDRAM, graphics double data rate 3 (GDDR3), and GDDR5.
In 2009, he joined Elpida (now part of
Micron Technology, Inc.), focusing on
GDDR5, GDDR5X, and GDDR6. He is a
member of the program committee of
the ESSCIRC and was a member of the
ISSCC program committee. He is a fellow at Micron.
Jennifer Taylor received her B.S.
degree in electrical engineering from
Rice University, Houston, Texas, in
1994 and her M.S. degree in electrical
engineering from Boise State University, Idaho, in 2004. She is currently
a principal design engineer at Micron
Technology Inc., Boise, Idaho, with a
focus on high-speed input/output circuitry. She holds 16 U.S. patents.
Justin Butterfield received his B.S.
and M.E. degrees in electrical engineering from Boise State University, Idaho,
in 2007 and 2012, respectively. He is
currently a senior engineer at Micron
Technology Inc. Boise, Idaho, on the
Silicon Signal Integrity team. He has
developed Input/Output Buffer Information Specification (IBIS) models for
the analysis of new memory standards,
including double data rate 5 (DDR5),
low-power DDR4 (LPDDR4), LPDDR5,
and open NAND flash interface. He is an
active member of the IBIS Open Forum
standards committee, with a focus on
improving IBIS interconnect modeling and the IBIS-Algorithmic Modeling
Interface for single-ended applications.

IEEE Solid-States Circuits Magazine - Spring 2019

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