IEEE Solid-States Circuits Magazine - Spring 2019 - 40
The application of DBI was shown to be an
effective method to enhance multiple key
aspects of the signaling.
in Figure 21. The data eyes were
measured at the DRAM signal vias,
and the jitters were captured corresponding to the DRAM receiver mask
width. When DBI was enabled, the DQ
jitter was reduced from 27.1% of the
unit interval to 22.1% in this system.
While the external measurements
served as an indication of the im provement, the actual jitter improvement
was characterized by two-dimensional
(2D) write-and-read eye shmoos based
on the setup in Figure 22. The position
of the DQ and DQS was scanned from
the center optimal point to the edges
of the unit or bit interval. In doing so,
the pass-and-fail region could be identified for each selected reference voltage of the receiver. This side-to-side
sweep was repeated over all the adjustable reference-voltage levels, and, by
combining these measurements, a 2D
eye shmoo was formed using a method
similar to that in [14].
Jitter ~ 22.1% UI
Jitter ~ 27.1% UI
(a)
(b)
FIGURE 21: The write-data eye (a) without DBI and (b) with DBI enabled. UI: unit interval.
DQ[7:0]
Write Margin
DQS_w
Delayed DQS_w
FPGA
DRAM
DQ[7:0]
Internal DQS_r
Read Margin
Delayed
Internal DQS_r
FIGURE 22: The write-and-read 2D data eye shmoo.
40
S P R I N G 2 0 19
DRAM Vref_i+1
DRAM Vref_i
DRAM Vref_i-1
IEEE SOLID-STATE CIRCUITS MAGAZINE
FPGA Vref_ j+1
FPGA Vref_ j
FPGA Vref_ j-1
The eye shmoo characterization
method provides a more accurate measure of the quality of the read-and-write
margins because it represents a true
measure of the system pass-and-fail conditions. In addition, the shmoo-timing
resolution can reach better than 5 ps per
step, while the adjustable voltage reference for the test is within 0.8% VDDQ.
Figure 23 shows the measured
eye shmoo with and without DBI in
both the read-and-write directions,
with the comparisons limited to the
optimal input-reference voltage setting. The gray regions highlight the
eye without DBI, while the outer blue
region in the horizontal bars shows
the improved eye widths.
In the write direction, the eye margin improved by approximately 7%
through DBI, while the read direction improved by roughly 11%. The
difference in eye-width improvement between the read and write
directions indicates that the relative power-noise improvement in the
FPGA (write) was different from the
DRAM (read). Part of the reason is that
the on-die capacitance on the particular DRAMs under test appeared
lower than the FPGA side. In addition,
the package inductance is lower than
that of the DRAM package; therefore,
IEEE Solid-States Circuits Magazine - Spring 2019
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2019
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