IEEE Solid-States Circuits Magazine - Spring 2019 - 43

lanes. As a result, a per-lane data rate
of 178 Gb/s is required to achieve a
target system bandwidth of 25 Tb/s.
Thus, there is strong motivation to
seek technologies that permit a finer
I/O pitch and more efficient use of the
available I/Os.
In addition, the electrical discontinuity of the package and board vias,
solder bumps, and balls impairs signal
integrity. Exacerbating this, as the number of I/O pins increases, the number of
PCB layers may also increase, thereby
introducing longer vias, more severe
discontinuities, and channel loss. This
additional channel loss is compensated
for through more complex equalization
circuitry, consuming a significant portion of the overall power.
Electrical board-level interconnects have also become a bottleneck
for optical links. For example, photonic modules for coherent optical
communication are helping line cards
process tens of terabytes per second.
However, once the optical signals are
converted to electrical signals, sending the data between chips on the
line card is expensive in terms of
power and area. Figure 1(b) shows
the board-level interconnect between
an optical module and a CMOS die.
The benefits of the low-loss and dense
optical interconnect are lost because
of the intervening PCB interconnect.
Thus, along with advancement in I/O
circuit design, improvements in packaging technologies are also required
for high-density I/O systems.
To address the issues of board-level
integration, ultra-short-reach (USR) links
provide an alternative approach for better energy efficiency, compact integration, and higher bandwidth density. USR
links traverse short, densely-packed
traces with few, if any, discontinuities
on a substrate shared by two or more
dies. They are useful when two functional blocks must exchange high-speed
broadband data, but it is desirable or
necessary to implement the functional
blocks in different technologies or
separate dies. Two possible packaging
substrates for USR links are the organic
packaging substrate and the silicon
interposer, both illustrated in Figure 2.

Both afford dense integration and commensurately short links with low channel loss compared to links using a PCB
interconnection, so they support much

better energy efficiency. Large solder
balls and PCB vias are unnecessary in
USR links, whose density is constrained
only by package design considerations,

Die A

Die B
150-200 µm

C4 Bump
Packaging
Substrate

Via

Solder Ball
PCB

0.5-1 mm

Channel
(a)
Optical Fiber
CMOS Die

Optoelectronics
150-200 µm

C4 Bump
Packaging
Substrate
Channel

Solder Ball

0.5-1 mm

PCB
(b)
FIGURE 1: The traditional board-level integration on a PCB: (a) CMOS die-to-die communication
and (b) CMOS die-to-optical-module communication. C4: controlled collapse chip connection.

Die A

Die B

Channel

C4 Bump

150-200 µm

Packaging
Substrate
0.5-1 mm

Solder Ball
PCB
(a)
Channel
µC4 Bump
Silicon
Interposer
C4 Bump

Die A

Die B

30-60 µm
TSV
150-200 µm

Packaging
Substrate
Solder
Ball

0.5-1 mm

PCB
(b)
FIGURE 2: Two mainstream packaging solutions for USR links: (a) sharing an organic packaging substrate between multiple chips and (b) using a silicon interposer on top of the packaging substrate to create the interconnects between multiple chips. TSV: through-silicon via.

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IEEE Solid-States Circuits Magazine - Spring 2019

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