IEEE Solid-States Circuits Magazine - Spring 2019 - 46

cylinders. Thus, neighboring bumps/
n vias with radius r, height h, and
edge-to-edge spacing s can be modeled as two parallel cylindrical wires
in media with permittivity f and
permeability n, and lumped circuit
elements can be used to model the
associated parasitics [14]. The bump
inductance (L Bump) and the via inductance (L Via) can be divided into two
components, namely the self-inductance (L s) and the mutual inductance
(L m), given by

Lm =

2rfh
C coax =
.
ln " (r + s) /r ,

2
C pkg2 = rfr ;1+ 2h $ ln ` rr j +1.7726.E.
rr
h
2h
(9)

To validate these equations, a complete link model is created. A distributed model of a stripline trace on an
organic packaging substrate is obtained
using the combination of a 2D field
solver and (1)-(4). Lumped models of
the parasitics at either end of the link
are included based on (5)-(9), using
dimensions of typical organic packaging substrates. The resulting model is
scalable for any length trace and amenable to rapid parametric sweeps. For
comparison, a 1-mm trace and equivalent pads and vias are modeled in a
3D electromagnetic simulator. Figure 5
shows that the simulation results of the
two approaches agree well.

(6)

When there are only one ground and
one supply voltage (VDD) neighboring
the bump [as shown in Figure 3(b)],
C Bump and C Via are given by
Cc =

ln c 2r + s +
2r

rfh
.
( 2r + s ) 2 - 1 m
2r
(7)

However, if there are multiple VDD and
ground bumps and vias surrounding
a signal, capacitances range from the
value calculated by (7) and the capacitance of a cylindrical conductor sur-

0

-20

-20

-0.2

-30

-30

FEXT (dB)

Insertion Loss (dB)

(8)

Using this equation, C pkg1 in Figure 3(b) can also be calculated. In
this case, s is the spacing between
the pad and the antipad (i.e., the circular ground conductor opening),
and h is the pad thickness. Finally,
C pkg2 is approximated using analytical equations from [15] for a disk-toplane capacitance:

2
nh
;ln ' h + c h m + 1 1
2r
r
r
2
- ` r j + 1 + r + 1 E, (5)
h
h 4
2
nh
;ln ' h + c h m + 1 1
2r
s
s
2
- ` s j + 1 + s E.
h
h

The model described in the previous section may be used to analyze
and compare the signal integrity of
single-ended and differential signaling schemes. We first compare 5-mm
silicon interposer traces. A stripline
geometry is adopted because it offers
more immunity to crosstalk than a
microstrip configuration. In total, four
different possibilities are evaluated in
terms of crosstalk and insertion loss.
Figure 6 shows their cross sections,
which maintain the same wire spacing (4 n m) in each case. Thus, differential signaling with ground shields
occupies more than twice the area
of the single-ended scheme. On the
other hand, Figure 7 shows four crosssections wherein the lane pitch is kept
constant at 12 n m per lane.
In this case, less spacing between
wires is available with differential
signaling. The insertion loss of the
four cases with and without the
per-lane pitch constraint is shown in
Figure 8(a) and (d). As shown in the
simulations results in Figure 8(b) and
(c), when there is no constraint on the
area required for die-to-die routing,
differential signaling with ground
shields provides the best immunity
to crosstalk, whereas single-ended
signaling shows the worst immunity
to crosstalk. However, once the laneto-lane pitch is limited, Figure 8(e)

-0.4
-0.6
-0.8

NEXT (dB)

Ls =

Single-Ended Signaling in USR
Communication

rounded by a coaxial hollow cylinder
conductor, given by

-40
-50
-60

0

5
10
15
20
Frequency (GHz)
(a)

25

-50
-60

-70

-1

-40

-70
0

5
10
15
20
Frequency (GHz)
(b)

Lumped Model

25

0

5
10
15
20
Frequency (GHz)
(c)

25

3D EM Model

FIGURE 5: A 3D electromagnetic simulation model versus a lumped element model for a 1-mm stripline: (a) insertion loss, (b) FEXT, and (c) NEXT.
EM: electromagnetic; FEXT: far-end crosstalk; NEXT: near-end crosstalk.

46

S P R I N G 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE



IEEE Solid-States Circuits Magazine - Spring 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2019

Contents
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