IEEE Solid-States Circuits Magazine - Spring 2019 - 55

signaling solution to maximize the
amount of information that can be
communicated within both spatial and
energy constraints. Given these constraints, single-ended (SE) signaling
offers the best solution when simultaneously optimizing across both
metrics because it requires only one
pin per signal compared to two pins
per signal with differential signaling,
which is used for most high-speed
chip-to-chip links. It is important to
emphasize that, while SE signaling sacrifices the advantages of differential
signaling, in limited usage scenarios
such as short-reach links, its more
efficient metrics provide advantages
over differential signaling. However,
as discussed in the following section,
densely routed SE signaling at several
tens of gigabits per second presents
many technical challenges. In response
to this, we developed low-swing SEsignaling techniques that provide high
energy efficiency when combined with
simple methods that carefully control
channel signal integrity.
In this article, we discuss how
ground-referenced signaling (GRS)
avoids many of the challenges associated with SE signaling, thanks to a
unique transmitter (Tx) topology, to
produce a link with high reliability,
high information density, and high energy efficiency for short-reach applications. GRS-based short-reach links also
use a simple but robust clock-forwarding scheme to cancel jitter without the
need for a clock recovery system at the
receiver (Rx), thereby, saving significant power. This approach also provides high-bandwidth jitter tracking,
which we take to the limit by matching
circuit delay and delay sensitivity for
clock and data lanes at both ends of
the link. Codesign of the link circuitry
and channel takes full advantage of
the ability to match the insertion delays of multiple data/clock lanes within the short-reach interconnect. The
low attenuation that can be achieved
in a codesigned channel is leveraged to
achieve a simple, robust, and low-power design. The most recent GRS-based
link introduces several innovations: 1)
a dynamic voltage scaling (DVS) power

pecially important because the NMOS
transistor is notably faster than the
PMOS transistor. In addition, this
termination scheme also allowed for
low-weight bus encoding to be used
to save power and reduce simultaneous switching output (SSO) noise [2].
(Low-weight bus encoding guarantees
that no more than 50% of the encoded
output signals can conduct current
simultaneously.) However, all of the
challenges associated with SE signaling remain in these systems.
The first challenge is that conventional SE systems require the generation of a reference voltage (VREF), as
shown in Figure 2(b), nominally halfway between the HI and LO signal
levels at the input to the Rx. There
are several ways to generate the reference voltage, and all produce some
amount of error (i.e., voltage reference uncertainty). This error is a fixed
noise source, and conventional SE
links must use sufficient signal amplitude to overcome the uncertainty. The
second challenge is that conventional
SE systems have a very complex and
frequency-dependent return path,
where their large signaling currents
flow through the on-chip power distribution network (PDN) [3], as shown
in Figure  2(c). The third challenge,
known as SSO noise, creates the single

supply regulator, which implements
the inverse of dynamic frequency scaling and holds link performance constant over process and temperature
variation; 2) link calibration circuitry,
which, once set at arbitrary supply
voltage and temperature, removes process variation and tracks subsequent
temperature changes without the need
for periodic recalibration; and 3) a fast
entry/exit pause mode that reduces
link standby power to about 25% of
active power, while holding entry/exit
times to <5 ns.

Challenges and Solutions
for SE Signaling
The fastest conventional SE systems
are those found in graphics memory interfaces [2], [3] employing the
signaling and termination scheme
shown in Figure 2(a). This approach
uses a voltage-mode driver, with series resistance (R DRIVE+ and R DRIVE- ),
to improve back-match to the channel and a termination resistor (R TERM)
connected to the supply (VDD) at the
Rx. When first introduced, this approach eased the transition from
the signaling used in main-memory
interfaces by providing a higher
common-mode (CM) voltage at the
Rx for the slow transistors found in
a dynamic RAM process, which is es-

MCM-GPU With Copackaged DRAM
GPU

GPU
GPU

GPU

GRS Links Over Package
Between GPUs
MCM-GPU Array

Optical Links

Optical Links

GRS Links Over PCB
FIGURE 1: The very short reach on-package (MCM) and short-reach off-package (PCB) link
examples. DRAM: dynamic RAM; GPU: graphics processing unit.

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IEEE Solid-States Circuits Magazine - Spring 2019

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