IEEE Solid-States Circuits Magazine - Spring 2019 - 62

link. The data lanes use I CLK, while
the forwarded clock lane uses Q CLK
to achieve a quadrature data-toclock timing relationship. The I CLK
and Q CLK distribution buffers are designed to have identical propagation
delays and power supply delay sensitivities. To preserve the quadrature
data-to-clock timing at the Rx input,

Tx
Data

Channel

Tx
ICLK

QCLK

Clock

all data and clock channels are routed with near identical lengths. This
ensures that the channels are delay
matched to a tolerance much smaller
than one bit period, or UI. At the receive end of the link, the data and
clock signals are amplified to CMOS
levels by identical amplifiers. The
clock Rx amplifier drives the root of

Rx
Tunable
Delay
δ

RxData

Data

CLK

RxClk

CLK
Buffer
Matched
Tx Delay

Matched Matched
Rx Delay Buffer
Delay

Matched
Channel
Delay

FIGURE 7: A delay-matched clock-forwarded link architecture with only one of eight data
lanes shown.

Vdd_IO
Digital
Regulator

PLL
Vreg_PLL

Vreg_IO
ICLK

RO
PD

÷2

(12.5 GHz) Data and Clock
Tx and Rx
QCLK

÷8

(a)
SS
TT
FF

Temperature (°C)

(b)

(c)

125
150

100

50
75

±4.1%
25

125
150

100

50
75

RO Current

-25

1.7
1.6
1.5
1.4
1.3
1.2

-50

Current (mA)

RO Voltage

-25

850
800
750
700
650
600

-50

Voltage (mV)

RefClk (1.56 GHz)

FIGURE 8: The DVS power supply regulation scheme: (a) the system schematic, (b) the RO
voltage, (c) the RO current. FF: fast-fast; SS: slow-slow; TT: typical-typical.

S P R I N G 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE

the Rx clock distribution buffer (RxClk) to provide sampling clocks at
each data Rx lane. In the data lanes,
adjustable full-swing CMOS delay elements are inserted between Rx amplifiers and samplers with an insertion
delay (d) designed to match that of
the Rx clock distribution buffer signal
(RxClk) at the midpoint of the adjustment range. Then, on a lane-by-lane
basis, each tunable delay element is
adjusted by trimming the internal
fan-out of the cascaded CMOS stages,
so that the insertion delay (d) tracks
that of the Rx clock distribution buffer. Duty factor is trimmed by adjusting the relative P-to-N transistor sizes
in the delay stages. The tunable delay
line provides ±10 ps of delay adjustment in 1.5-ps steps to each lane,
which may be used to compensate
for ±1.5-mm trace-length mismatch
between each data lane and the forwarded clock lane. The delay range
and step size do not vary significantly with PVT, thanks to the DVS supply
regulation scheme.
The use of near-identical circuitry for transmitting and receiving
both the forwarded clock and data
signals, in addition to delay-length
matching of all channels, ensures
that the data and clock insertion
delays are matched across the entire
link and track across variations in
PVT. This simple mechanism cancels
nearly all sources of jitter, including
power-supply-induced jitter, over
a frequency range approaching the
link bandwidth. Additionally, the
jitter requirements of the PLL are
greatly relaxed because any timing variations are common between
the relative timing of the data and
clock signals.

DVS Regulation Scheme
Our latest version of the GRS link
employs the DVS power supply regulation scheme shown in Figure 8(a),
which uses a novel regulator described
in detail in [6]. At the expense of regulator losses, this arrangement varies
the internal I/O supply voltage to
flatten circuit speed across PVT and
reduce current consumption variation

IEEE Solid-States Circuits Magazine - Spring 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2019