IEEE Solid-States Circuits Magazine - Spring 2019 - 70

The C-PHY interface introduces the concept of
multiphase encoding to help eliminate the need
for transmitting a forwarded clock, thus also
saving on wire count.
solution to transmit more bits of data
per physical conductor in a given
time interval, thus making it somewhat unique compared to traditional
digital buses. As shown in Figure 1(a),
a typical digital communication link
consists of a differential data buffer
for encoding the digital bits being
transmitted and a differential clock
buffer for encoding a timing synchronization signal, which is also transmitted and used by the receiver for
sampling the data bits.
The sampling operation itself is
performed using a D flip-flop clocked
by the timing synchronization signal
coming from the clock buffer. The
result of this traditional architecture is
that four separate conductors (wires)
are used to transmit only a single bit of
data in a given unit time interval (UI).

The C-PHY interface fundamentally
solves this apparent inefficiency in the
number of wires by attempting to generalize the forwarded clock differential
pair architecture of Figure 1(a). Just as a
differential pair exploits two wires to
work together in encoding a physical
quantity representing a logic bit, this
standard explores the possibility of
using a group of wires (more than two)
in concert to encode/transmit more
than 1 b of data per UI. This abstract
concept is shown in Figure 1(b) and
is referred to in this article as a
generalized multiconductor transmission solution.
In performing this generalization,
the C-PHY interface deploys innovative signaling methods that rely on a
hybrid single-ended/differential-signaling scheme and multilevel signal

Data P/N
(Differential)

D Q

Clock P/N
(Differential)
(a)

Multiconductor
Encoding
Circuit

Multiconductor
Maximum
Likelihood
Receiver Circuit

(b)
FIGURE 1: A C-PHY trio is best seen as a generalized multiconductor transmission solution.
(a) A typical digital communication link. (b) A generalized multiconductor transmission solution.

S P R I N G 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE

modulation. Therefore, it departs considerably from the traditional twolevel differential voltage modulation
architecture. Additionally, it introduces the concept of multiphase
encoding to help eliminate the need
for transmitting a forwarded clock,
thus also saving on wire count. In
this article, we introduce these concepts along with the implications they
have on circuit-level implementation
in advanced digital fabrication processes. We first discuss the concept
of three-phase encoding and then
describe the driver-circuit implementations required to achieve this encoding method. Subsequently, we describe
receiver circuits and the all-important
topic of clock recovery in the context
of three-phase encoding. Finally, we
describe the higher-level mapping
techniques deployed in C-PHY, which
result in pleasantly surprising flexibility at the protocol levels.

Three-Phase Encoding
As a first practical incarnation of its
underlying multiphase communication technique [7], C-PHY achieves the
generalization in Figure 1(b) by implementing a three-phase encoded transmission system using three wires. In
this system, three wires work in concert to create a synchronous data link
that achieves a throughput of approximately 2.3 b/unit. This already represents a large improvement over the
1-b/UI in a legacy differential data
link, and it uses fewer wires (three
instead of four).
The conceptual circuit diagram
for a three-phase encoded C-PHY link
is shown in Figure 2. A C-PHY bus is
both single ended and differential,
with the distinction occurring only in
whether the system is viewed from
the transmitter or receiver point of
view. When viewed at the transmitter
side, the C-PHY bus is clearly single
ended. Three single-ended phasematched drivers are used to modulate
the voltage potentials on the transmission medium (a trio of three individual wires). However, when viewed
at the receiver side, the C-PHY standard is fully differential. Specifically,

IEEE Solid-States Circuits Magazine - Spring 2019

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