IEEE Solid-States Circuits Magazine - Spring 2019 - 73

must wonder whether the voltage
mode driver is expected to drive the
middle level (force a potential voltage on the line) or to leave the line
floating. To a first order, there is no
need to actively drive a middle level;
and it is sufficient to simply float the
line (disconnect both up and down
transistors in the driver). The reason is that C-PHY requires receiver
termination at the other end of the
transmission line, thus minimizing
reflections; as we will show shortly,
receiver termination can guarantee
the generation of the middle level.
More precisely, the wire encoding
mechanisms described previously
guarantee that floating the up and
down transistors in the driver circuit
will result in a mid-level nominal
voltage. Practically, however, floating the up and down transistors does
not offer proper back termination,
which translates into a potentially
severe return-loss issue in a live
system. Therefore, for high-speed
applications, it is always better to
actively drive the middle level in a
C-PHY link.

A switching event at each of the single-ended
drivers translates into a wave that propagates
along the transmission lines defined by the
wires and their reference planes.
A Word About Termination
and Signal Trace Routing
In the previous section, we mentioned that the wire encoding mechanisms guarantee that the average
level of the three wires in C-PHY
remains constant. However, we did
not explain what the circuit implementation for this was, nor did we
explain why this allows for floating the driver circuit when encoding a middle level. In this section,
we elaborate on this topic with the
help of Figure 7, which illustrates
how the C-PHY receiver terminates
the single-ended transmission lines
of a trio. In Figure 7(a), when the A
wire is high and the B wire is low,
one can hypothetically imagine this
pair of wires acting as a regular differential pair. If each of these two
wires is terminated with a floating

Note
It may be useful at this juncture to make a small digression regarding the
perceived multilevel waveforms in C-PHY. Creating an eye diagram from a
C-PHY receiver waveform results in an image like that shown in Figure S1.
This eye diagram appears very similar to a four-level PAM signal (PAM4),
which is a modulation scheme gaining traction in 400-G applications,
among others. Unlike PAM4, the outer eyes in C-PHY are completely irrelevant. The gain in number of encoded bits per UI is achieved through the
entire encoding and mapping scheme of C-PHY, not through multilevel
signaling in and of itself.

load resistor equal to the characteristic impedance of the transmission
line and equal to the source impedance of each driver, it is easy to see
that the midpoint between the two R L
resistors on these two transmission
lines will settle to a common-mode
voltage level equal to the average of
the two wires (nominally +V/2) . We
can call this midpoint the common
point of the trio. Then, regardless
of whether or not wire C is driven to
the middle level by its up/down transistors, there will be no dc current
flowing through the wire (assuming nominal transistor and resistor
parameters, of course).
Specifically, if the up/down transistors are floated, then there is no
dc path on the driver side, and the
entire wire will be held to the middle
potential voltage created by the combination of the A and B wire termination resistors R L. Similarly, if the up/
down transistors are driven to set up
a middle potential, then this potential level will be equal to that set by
the two R L resistors of wires A and
B, thus resulting in no dc current
flow, at least to a first order. From a
dc point of view, a common-point termination is consistent with the threephase encoding scheme where the

+V
Irrelevant
Logic 1

Differential
Receiver
Decision
Threshold

Eye Opening
Logic 0
Irrelevant

FIGURE S1: A C-PHY eye diagram.

Data

Down
(a)

(b)

FIGURE 6: (a) One leg of a differentialvoltage-mode driver, and (b) one leg of a
three-phase encoded trio.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 19

IEEE Solid-States Circuits Magazine - Spring 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Spring 2019