IEEE Solid-States Circuits Magazine - Spring 2019 - 82

puts 5 b over six wires [i.e., (5b6w)]
[17], [18].

tal converter (ADC) circuits are ideal
encoders and decoders for this type
of signaling. To implement PAM N,
data converters with a resolution of
at least log 2 (N - 1) are required to
implement the transceiver. Therefore, ADCs and DACs are matched
circuits (i.e., matched hardware) for
implementing PAM. The required
resolution of the data converters
must be more than log 2 (N - 1) to realize proper equalization. Because
CS is not based on AM, the matchedhardware topolog y used for the
receiver and transmitter is also different from DACs and ADCs.

Transceiver Architecture
Designing high-speed, energy-efficient transceiver circuitry is a major
challenge for high data-rate serial
communications. Any complexity in
the signaling method used to implement the system will directly affect
circuit performance and efficiency.
Therefore, any proposal for implementing signaling methods should
be carefully studied so as to minimize circuit-level complexities. For
example, PAM-4 signaling requires a
complex transmitter and receiver architecture to amplify, equalize, and
slice the data. PAM signaling is based
on coding data in the amplitude of
the signal; hence, digital-to-analog
converter (DAC) and analog-to-digi-

Matched-Hardware Signaling
As mentioned previously, CS is orthogonal and designed to carefully
keep the ISI ratio as close as possible to 1. Therefore, the matched-

w0
b0

Rx Front End

Encoder

w1
w2

+
+

+
-

+
+

+
-

+
+

+
-

Quaternary
on Wires

Binary at
Slicer Input

FIGURE 8: A chord transceiver based on ENRZ signaling.

B2,B2
B1,B1
B0,B0

VDD
VBP

Linear Encoder
and Output Driver
VSS

+ VOUT -

(a)

w<2>

w<1>

w<3>

w<0>

Linear
Decoder

(b)

FIGURE 9: The (a) ENRZ transmitter encoder and (b) MIC circuit topology [2], [19]. The remaining circuitry on the transmitter or receiver side is similar to conventional differential PAM-2
systems. The logic combination in the transmitter (driver) and receiver (MIC) vary depending
on the wire or subchannel.

S P R I N G 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE

circuit topologies used for CS may
be described by the matrix transformation governing the signaling
method. If a different circuit topology is used, it is possible to degrade
the ISI ratio and fail to provide the
inherent signal integrity expected
from CS. For example, a differential
pair matches well to the transformation described in Figure 6. A differential pair is a linear combiner that can
take VCM and data and produce the
desired differential output. Alternatively, a differential pair can receive
VCM + D and VCM - D at its input and
produce the decoded data at its output. This linear combination happens
in both cases in the analog domain
and does not add any latency. As a
generalized form of DS, the same approach is valid in CS, whereas both
the encoder and decoder are combinational analog circuits. On the
transmitter side, the digital bits are
fed into an analog combiner [such as
a single-side terminated (SST) driver], which produces the wire values.
Those wire values on the other end
are received by front-end linear combiners, which produce binary values
at their outputs. All of the circuits
before the final stage of the transmitter and after the first stage of the receiver remain the relatively simple,
conventional circuits used for differential systems.
Figure 8 shows one example for
ENRZ signaling. The three input bits
on the transmitter side are fed into an
analog encoder and launched onto the
wires. The signals over the wires are
all multilevel. On the receiver side,
MICs or MI combiners are used to convert the multiwire, multivalue signals
to binary voltages. The circuit topology of the following equalizer and
slicer blocks will be very similar to a
conventional differential system.
Figure 9(a) shows an exemplary
implementation of ENRZ transmitter and receiver analog combiners.
The encoder is a simple SST driver
that receives three input bits (B 0, B 1,
and B 2) . The output of each wire is
a proper linear combination of these
bits placed on the four-output wires.

IEEE Solid-States Circuits Magazine - Spring 2019

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