IEEE Solid-States Circuits Magazine - Spring 2019 - 83

The circuit used to decode the wire
values inside the receiver is shown
in Figure 9(a). The combination of
the four wire values (W < 3: 0> ) is calculated, and a binary output ( VOUT)
is produced. The linear encoder and
decoder circuits are implemented
in the analog domain with no additional latency, and no digital domain
encoding or decoding is required.
Both circuit diagrams in Figure 9
match the matrix transformation
illustrated in Figure 7(a). Figure 10(a)
and (b) shows the analog encoder
(transmitter) and decoder (receiver)
for 5-b, 6-w CNRZ signaling; these
are very similar to the ENRZ encoder
and decoder. The binary bits are fed
into five linear encoders [see Figure 10(a)], while a multivalue signal
is placed on the wire. On the receiver
side, the multilevel signal is received
at the input of a linear decoder, while
the output is binary.
Figure 11(a) illustrates a transceiver fabricated in 28 nm that can
transfer data at 20.83 Gb/s/w (effective BW) while consuming 0.94 pJ/b
and using CNRZ signaling, which
sends 5 b over six wires (PE = 5/6).
Figure 11(b) shows the bathtub for
the five output bits (called five subchannels) as well as a sample eye diagram, exhibiting a more than 12-ps
opening at 1E-15 BER. The proposed
transceiver employs a clock-forwarding scheme to enhance the link's
jitter tolerance and reduce power
consumption [20].

If more spectrum-efficient signaling is required
for 112 Gb/s and above, then multitone signaling
can be employed.

Based on Figure 7(a) and (b), the
transmitted data are distributed
over multiple wires; therefore, the
transmitted data can still be reconstructed accurately if there is low
skew between wires. When the skew
is high, however, the eye closure
can be considerable. In this case, a
skew-correction circuit must be employed on either the transmitter or
receiver side. Implementing a skewcorrection circuit on the transmitter
side is more convenient; however, it
requires a backchannel communication mechanism. Otherwise, the
receiver-side skew correction can be
employed to adjust the signal skew
in front of the MIC.

Summary and Future Directions
There is growing demand to increase
data-transfer BW in the HPC industry.
Applications such as autonomous
driving require continuous data
movement between the memory and
processor at rates many times faster
than what is available today, as well
as with much lower power consumption. Today's wireline industry is
mainly based on PAM signaling, with
PAM-2 being the most dominant mod-

ulation scheme below 56 Gb/s and
PAM-4 as the basis for most links at
higher data rates [Figure 12(a)]. There
are current reports that demonstrate
112 Gb/s using PAM-4 to implement
high-precision DACs and ADCs for
encoding and decoding purposes as
well as for equalization [11], [12].
To date, there has been no demonstrated use of PAM-4 or higher-order
PAM that achieves data rates as high
as 224 or 448 Gb/s.
CS, however, proposes a different road map. Based on the theory
of CS, the number of levels at the
slicer input should be minimized.
Figure 12(b) shows the copper wireline
communication road map based on this
approach. At low data rates (such as 16
and 28 Gb/s), differential binary (the
simplest form of CS) has proven to be
a very good choice. Differential binary
signaling (PAM-2) can be implemented
using reasonably simple transmitter
and receiver circuits. For higher data
rates (e.g., 56 Gb/s and beyond), the
sampling-clock frequency as well
a s c h a n nel loss becomes excessively large. Therefore, a more spectrum-efficient signaling is required.
If multiwire signaling is possible,

VDD
VBP

Linear Encoder
and Output Driver
(a)

VSS

RL

+ VOUT -

w<5>

w<2>

w<4>

w<3>
w<1>

Linear
Decoder

w<0>

CS uses spatial coding (multiwire
coding) to enhance data throughput without compromising sensitivity to ISI. Interwire skew is a main
issue with any kind of multiwire
signaling, even differential PAM-2,
the simplest form of CS. Any skew
between wires will cause intersubchannel interference, which means
that a portion of the information
from one subchannel penetrates
other subchannels, resulting in eye
closure. When interwire skew is low
(e.g., 10% of a unit interval or lower),
its effect can generally be ignored.

B4,B4
B3,B3
B2,B2
B1,B1
B0,B0

Sensitivity Skew

RL

(b)

FIGURE 10: The (a) CNRZ transmitter encoder and (b) MIC circuit topology [2], [19]. The
remaining circuitry on the transmitter or receiver side is similar to conventional differential
PAM-2 systems. The logic combination in the transmitter (driver) and receiver (MIC) vary
depending on the wire or subchannel.

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IEEE Solid-States Circuits Magazine - Spring 2019

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