IEEE Solid-States Circuits Magazine - Fall 2019 - 11

Another advantage of differential
rings is that they can provide multiple phases having a minimum spacing equal to r divided by an even
number. This is possible because a
differential ring with an even N can
still have negative feedback at low
frequencies.

0.5I SS R D = 300 mV. The transistors
do not enter the triode region, a point
to which we return later in the context
of flicker noise. The phase noise displays a slope of nearly -30 dB/dec from
100-kHz offset to 1-MHz offset and
-20 dB/dec thereafter. That is, flicker
noise upconversion is much less pronounced here. Linear scaling can also

be applied to the differential ring by
multiplying W 1, 2 and ISS by a factor of
M and dividing RD by the same factor.
Let us now compare the two designs. Why is the supply sensitivity
of the first ring so much higher than
that of the second? This is because
the supply dependence of the delay is
different in the two designs. In an inverter, the drive strength depends on
VDD; that is, the drain current and onresistance of the transistors directly
and substantially change as VDD fluctuates. In a differential pair, on the other
hand, the load resistance is relatively
constant, and only the capacitance has
a slight supply dependence. Illustrated
in Figure 6, this effect arises from the
nonlinear drain-bulk capacitance, CDB,
of M1 and M2, which varies with the
common-mode voltage at X and Y and,
hence, with VDD.
To compare the phase-noise profiles fairly, we must normalize them
to the oscillation frequency and the
power consumption. This can be accomplished by defining a figure of
merit (FOM) as follows:

Performance Studies
N Stages
CL

FIGURE 2: A ring oscillator consisting of
N inverters.

+-
-+

VDD
CL
Vin1

RD
X

RD
Y

FOM = 10 log

Vin2

FIGURE 3: A three-stage differential
ring oscillator.

W = 120 nm
R
L N 40 nm

W = 240 nm
R
L P
40 nm

f 02
,
Df PmW S zn (Df )
2

(1)

where Df denotes the offset frequency at which the phase noise, S zn (Df ),
is measured and P mW is the power
consumption expressed in milliwatts.
Table 1 summarizes the two oscillators' performance parameters. As a

ISS

0.2 fF
(a)
0
Phase Noise (dBc/Hz)

1.2
1
Amplitude (V)

We wish to quantitatively study the
behavior of inverter-based and differential ring oscillators and compare
their performance in terms of phase
noise, power consumption, and supply sensitivity. We design the two for
roughly the same oscillation frequency in 40-nm technology and simulate
them in the slow-slow corner at 75 °C
and with a worst-case supply voltage
of 0.95 V. We also include some explicit load capacitance at each node as an
estimate of the layout parasitics.
Figure 4 depicts the inverter-based
ring along with its waveform and
phase-noise profile. The circuit runs at
f0 = 22.6 GHz, draws 57 nW, and exhibits a KVDD of 50.2 GHz/V, a very large
value. The phase noise falls with a
slope of approximately 30 dB/dec
from 100-kHz offset to 100-MHz offset, revealing the dominance of upconverted flicker noise.
The phase noise is excessively high,
but it can be simply traded for power by
"linear scaling": if we multiply the widths
of all of the transistors by M, f0 and the
supply sensitivity remain constant (if
the layout parasitics are scaled) while
the power consumption rises by the
same factor and the phase noise falls
by 10 log M . For example, selecting
(W/L) N = (100 # 120 nm)/40 nm and
(W/L) P = (100 # 240 nm)/40 nm raises the power to 5.7 mW and reduces
the phase noise at 1-MHz offset from
-47 dBc/Hz to -67 dBc/Hz. Of course,
the area also grows proportionally.
Shown in Figure 5 are the differential
ring, its waveforms, and its phase-noise
profile. Operating at f0 = 20.8 GHz,
the oscillator consumes 285 μW and
has a KVDD of 1.82 GHz/V. We recognize that VX and VY do not have time
to reach VDD = 0.95 V, and the single-ended voltage swing is 270 mVpp,
somewhat close to our estimate of

0.8
0.6
0.4
0.2
0
−0.2

0.05

0.1
Time (ns)
(b)

0.15

−20
−40
−60
−80
−100
−120
105

106
107
Offset Frequency (Hz)

108

(c)

FIGURE 4: (a) A ring oscillator design example, (b) its waveform, and (c) its phase-noise profile.

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IEEE Solid-States Circuits Magazine - Fall 2019

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