IEEE Solid-States Circuits Magazine - Fall 2019 - 13

Inv1

Inv2

C

A

B
D

Inv4

Inv1

C

Inv8

Inv7

Inv3

Inv2

Inv1 - Inv4:
240 nm
W
Q R =
L N 40 nm

B

Q

Inv5

Inv6

(a)
Inv1

A

Inv5

C

Inv2

Inv7

Inv3

D

Inv8

Q
(a)
B

C

(b)

Inv3

Inv2

B

Inv8 Inv5

Inv7

Inv3

D

D

Inv4

Voltage (V)

Inv4

Inv6

A

(c)

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1

W = 240 nm
R
L P
40 nm

−20

A

C

B

D

Phase Noise (dBc/Hz)

Inv6

Inv1

Inv5 - Inv8:
120 nm
W
Q R =
L N 40 nm

A

Inv4

W = 480 nm
R
L P
40 nm

−40
−60
−80

−100

18.9

19 19.1 19.2 19.3
Time (ns)
(b)

−120
105

106
107
Frequency (Hz)
(c)

108

FIGURE 7: (a) A four-stage ring. (b) The addition of cross-coupled inverters to avoid latch-up.
(c) A redrawing of the topology in (b).

FIGURE 8: (a) A quadrature oscillator design example, (b) its output waveforms, and (c) its
phase noise.

This expression assumes that the
single-ended voltage swing is equal to
I SS R D . We observe that S zn rises if ISS
falls and I SS R D remains constant. According to simulations, the increase
in the swing and the decrease in ISS
partially cancel each other, yielding
a 1-dB degradation in the FOM for
the four-stage differential ring.
We next turn to the inverter-based
oscillator of Figure 2 and ask how it
can be modified to provide quadrature outputs. Let us begin with the
four-stage loop shown in Figure 7(a).
Ignoring for the moment the inversion provided by each stage, we recognize that the circuit can oscillate at
a frequency f0 = 1/ (8TD) . Thus, A and
B carry complementary waveforms,
and so do C and D. Also, the latter
two are 90° out of phase with respect
to the former two. From another perspective, the loop consists of four
one-pole stages, thereby generating
90° phase separations between consecutive nodes-if it oscillates.

Unfortunately, the circuit of Figure 7(a) prefers to latch up: the loop
can indefinitely maintain A = B = 1
and C = D = 0 or vice versa. We must,
therefore, devise a mechanism that
avoids this condition. For example,
we can tie a circuit between A and B
to discourage them from reaching the
same state. Such a circuit is readily
realized by a pair of cross-coupled inverters because they fight equal logical states at their input and output
nodes. This point leads to the structure depicted in Figure 7(b), often redrawn as in Figure 7(c). The topology
was reported in [6].
How should the cross-coupled inverters be sized with respect to those
in the main loop? The former must
fight the latter if Inv1−Inv4 tend toward latch-up. From this perspective,
Inv5−Inv8 should be strong enough.
On the other hand, these inverters
also fight Inv1−Inv4 during transitions, both draining power and injecting noise. Thus, Inv5−Inv8 should

not be excessively strong. As a rule
of thumb, we choose a ratio of two
between the strengths of Inv1−Inv4
and those of Inv5−Inv8. Greater ratios
run the risk of latch-up in the presence of mismatches, and lower ratios
degrade the FOM.
Let us design the circuit of Figure 7(b)
and study its performance. Returning
to our ring design in Figure 4(a) and assuming a minimum allowable width of
120 nm for the transistors, we choose for
the main inverters (W/L) N = 240 nm/
40 nm and (W/L) P = 480 nm/40 nm
and for the cross-coupled inverters (W/L) N = 120 nm/40 nm and
(W/L) P = 240 nm/40 nm [Figure 8(a)].
Plotted in Figure 8(b), the quadrature
waveforms exhibit a slight swing degradation due to the fight between the
main and cross-coupled inverters. The
oscillation frequency, f0, is equal to
26.5 GHz, and the supply current is
235 nA.

IEEE SOLID-STATE CIRCUITS MAGAZINE

(continued on p. 81)

FA L L 2 0 19

13
IEEE Solid-States Circuits Magazine - Fall 2019

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