IEEE Solid-States Circuits Magazine - Fall 2019 - 59

comparing it to its predecessors by
creating actual designs and analyz-
ing the results.
The significant amount of data that
exists for a design based on a previ-
ous technology offers the advantage
of providing a converged design and
a variety of design types. Often, our
integer and floating-point datapaths
will have different design characteris-
tics compared to the instruction and
data caches as well as the decoding
and scheduling units. Some examples
of those differences include the exis-
tence or lack of SRAM arrays, aspect
ratio, number of repeaters, upper-
level metal usage, and overall cell uti-
lization. Gathering data across all of
the converged designs can provide
valuable insights that are more dif-
ficult to get when ramping up a new
process technology. A small design is
initially used to verify that the PDK,
electronic design automation tools,
and overall environment work cor-
rectly. In addition, it can be used for
many quick iterations and experi-
ments. Once confidence in the initial
results is confirmed, a larger design
or designs can be employed to assess
the technology's capabilities.

Technology Trends and ProcessDefinition DTCO
As the industry continues to scale
process geometries beyond 7 nm, the
manufacturing complexity drives sig-
nificant challenges [7] that can be man-
aged with the use of more restrictive
design rules. In addition, geometric
scaling puts pressure on the electrical

120

Fundamental technology scaling is not
keeping pace with Moore's law, and other
design options are necessary to continue the
historical trend.
and reliability characteristics. Funda-
mental technology scaling is not keep-
ing pace with Moore's law, and other
design options are necessary to con-
tinue the historical trend. Each of these
areas requires a tight collaboration
between the technology and design to
achieve an optimal product.
One concern for high-performance
designs, moving forward, is the signifi-
cant resistance increase of the smallest-
pitch via and metal layers, as shown
in Figure 2. The metal layers higher
in the stack are often ported from the
prior technology. For those upper met-
als, the wire resistor-capacitator (RC)
delay is reduced at the same rate as the
design-area scaling. A pitch reduction
of 1× metal layers is key to enabling
area scaling but comes at a significant
resistance cost.
Current process technologies typi-
cally use copper interconnects with a
barrier layer that separates the copper
from the surrounding silicon. As the
width of those metals is reduced, the
barrier layer, which is highly resistive,
becomes a larger percentage of the
total wire volume, increasing the resis-
tance per unit length at a rate greater
than the width scaling. As shown in
Figure 3, that results in a lower metal-
wire delay, which represents a more

Google Search Results for DTCO

100
80
60
40
20
0
2004 2006 2008 2010 2012 2014 2016 2018 2020
Year
FIGURE 1: The trends in DTCO papers.

significant delay component and shifts
the overall wire-delay-layer sensitiv-
ity lower in the metal stack. Due to
that shift, standard wire-engineering
techniques for wire-dominated criti-
cal paths, which previously succeeded
through the use of higher-quality
routes further up the stack and also
of nondefault routes (NDRs) lower in
the stack, have become less effective.
While using NDRs in the critical lower
metal layers would be beneficial due
to the process complexities at very
small geometries, these technologies
have significant restrictions with regard
to any use of a nonminimum width
or spacing. This interaction between
technology limitations and design
requirements is a good example of the
importance of early, upfront collabora-
tion to come to an optimized solution.
Another option to reduce the resis-
tance impact is the use of new materials.
Cobalt is being introduced at the 10-nm
node as a copper replacement [8] for the
smallest-pitch metals. While cobalt has
a higher natural resistivity than cop-
per, it does not require a barrier layer
and therefore has a lower resistance
per unit length at very tight widths.
Cobalt also has the benefit of improved
electromigration, which could still be a
concern for copper wires, particularly

Technology Node Scaling
6

Via Resistance

5
4
3
Wire RC Delay

2
1
0

FIGURE 2: The estimated trends across five technology generations.

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IEEE Solid-States Circuits Magazine - Fall 2019

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