IEEE Solid-States Circuits Magazine - Fall 2019 - 60

The via resistance between the lowest layers
is a significant concern as we continue to scale
dimensions to even smaller values.
those used for power delivery. While
the choice of copper versus cobalt and
other more exotic materials is not left as
an option for the design consumer, the
process definition would be influenced
by collaboration with key customers to
ensure that the right choice was made.
Several additional trends relate to
the lithographic challenges imposed as
feature sizes continue to be reduced.
As geometries scaled below the 193-nm
wavelength of the immersion lithography tools, it became necessary to
add process constraints to the development of new innovations. One constraint transitioned the critical layers
from bidirectional layouts, which can
be routed vertically or horizontally, to a
restricted, single direction. Some technologies may be quasi-unidirectional,
in which routing support for the nonpreferred direction is possible but at
great expense. The concern is that the
process window at aggressive pitches
is small. The technology is optimized
for the minimum pitch, often with only
a few discrete line widths and spaces
allowed. These restrictions must be
accounted for in the development of
track plans and power grids.
Unidirectional patterning was first
introduced for polysilicon in the 65-nm
node [9]. Later nodes have continued
the trend toward small-pitch metal layers. Restricting patterns so that they

are unidirectional eliminates manufacturing concerns related to jogs, which
are difficult to properly pattern and
typically require a significant additional metal width to ensure proper
patterning, due to the rounding of the
corners. However, there are advantages
to enabling jogs on the lowest critical
layers. As previously discussed, the via
resistance between the lowest layers is
a significant concern as we continue
to scale dimensions to even smaller
values. Enabling metal jogs to make a
connection to a net on a different signal track can eliminate the need to via
up and down to another metal layer to
make the connection using only unidirectional metals. That could improve
the overall delay by removing the additional series-via resistances, trading
that off against the process concerns
related to supporting jogs.
Another innovation to enable the
continued process scaling constrained
by lithography is multipatterning,
which was introduced in the 22-nm
node [10]. In this case, a single layer
can be split into multiple patterns, or
"colors," at a relaxed pitch, which the
lithography tool is then capable of
processing. There may be design optimizations that can be leveraged for
particular colors, depending on the
process method used to implement
the multipatterning. For example,

Wire RC Contribution by Layer

when using self-aligned double patterning, the electrical characteristics
of the two colors may not be equivalent. In that case, design optimization
may be able to take advantage of the
electrical differences (for example,
routing the power grid or critical nets
on the color with the lower resistance).
Multipatterning is also routinely
used for via creation. A higher number
of patterns for a given layer allows a
tighter pitch to be supported. As illustrated in Figure 4, the tighter pitch
enables a higher density of vias, potentially improving the overall via resistance by enabling more double-cut
vias or resulting in an improved design
routability. However, the larger number of patterns comes at a cost, as the
number of masks and steps necessary
to pattern the full layer increases. Thus,
a tradeoff exists between the minimum
via spacing and the die cost. DTCO is
useful for determining whether the
improved via spacing enabled by a multipatterned layer is justified based on
the potential area savings that may be
realized due to the ability to have more
net connections in closer proximity.
After a decade of development,
extreme ultraviolet (EUV) steppers have
been announced for use at the 7-nm
node and beyond, replacing 193-nm
immersion lithography [11]. While the
transition will help to alleviate the need
for multipatterning in the initial node, it
will only be a short time before the continuing process pitch-scaling pushes
the technology to support multipatterning using EUV to support even tighter
pitches. EUV has a set of tradeoffs to be

Double-Pattern
Via Minimum Space

25 M1
(%)

20
15
10
Mlast

Single-Pattern
Via Minimum Space

0
FIGURE 3: The high-performance CPU average wire delay sensitivity for a projected 5-nm
technology.

FA L L 2 0 19

IEEE SOLID-STATE CIRCUITS MAGAZINE

FIGURE 4: The connection density advantage of a double-patterned via.

IEEE Solid-States Circuits Magazine - Fall 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2019