IEEE Solid-States Circuits Magazine - Fall 2019 - 61

analyzed that are similar to the multi-
patterning described previously. Due to
the complexity and relative immaturity
of EUV, layers that require it for man-
ufacturing are very expensive. DTCO
work is beneficial to evaluate the trad-
eoffs in pitch reduction versus area sav-
ings, which can then be weighed against
the overall product cost.
In addition to the tradeoffs dis-
cussed previously, the introduction
of chiplet-based architectures [12]
gave designers the ability to custom-
ize each chiplet to its optimal technol-
ogy. Whereas, in the past, a monolithic
design may have offered a compro-
mise between the differing require-
ments across a chip, new packaging
technologies enable independent tech-
nology optimization.

Standard Cell Design
Standard cell development evolves
with and influences technology. While
standard cells must follow the tech-
nology definition, they are an integral
source of early design feedback that
can influence changes. Early design
technology co-optimization is needed
to identify significant design com-
plications so that the technology can
be adjusted to mitigate the issues.
An example could be the early lay-
out effort on critical combinational
and sequential cells, where the stan-
dard cell team is finding a particular
design rule that is hindering the cell
density or routability. The standard
cell team can provide this feedback
to the technology team to determine
whether the design rule can be relaxed
to improve cell scalability. That early
feedback is crucial to developing a
technology that provides a maximum
benefit to customers.
Once the technology has been
defined, the suite of standard cell
library options to be offered must be
defined. Determining which is best
suited to a project's goals depends
largely on the power, performance,
and area targets. A denser standard
cell library that delivers an optimal
area and power efficiency can be
more favorable for low-power mobile
designs, while a standard cell library

Early feedback is crucial to developing a
technology that provides a maximum benefit
to customers.
that is less dense, has a higher drive
strength, and delivers optimal per-
formance may be more favorable for
high-frequency designs.
Many factors should be consid-
ered when choosing a standard cell
library, including the cell height, elec-
trical requirements, and routability.
Determining the standard cell height
is one of the initial metrics that must
be defined. The height determines the
drive of the cell, the power/ground
delivery to the cell, and the number
of usable routing tracks. A taller cell
height indicates a stronger minimum
drive strength, which is advantageous
for high-performance designs, but it
comes at a higher area and power cost.
A taller, higher-drive-strength cell will
draw more current, which can have
negative impacts on electromigration
that may require additional routing
to mitigate. The additional routing to
mitigate electromigration can lead to
a higher overall switching capacitance
at the design level that is not captured
in the cell-level analysis.
Standard cell height can also have
a significant impact on routability and
pin accessibility. A smaller, denser cell
can be more difficult to route and lead
to pin-accessibility issues. As a result,
more cells in a high-density library
may need to be changed from a single-
row height to a double-row height to
make the pins more accessible. This
cell aspect-ratio change often comes at
an area and sometimes a performance
cost, so some of the area savings in a
high-density library may be lost if a
significant number of cells needs to
be changed from single-row to double-
row height. By contrast, a taller cell in
a less dense library may enable addi-
tional routing tracks, improving pin
accessibility and the overall routability
of the design. Improving standard cell
pin accessibility results in fewer design-
rule checks (DRCs) in a routed design
and can improve the route-run time.

Once a standard cell library has
been chosen, it must be closely evalu-
ated to find cell-specific problems
and provide feedback to the foundry
or vendor. Some important areas of
investigation include cell area and
performance optimization, power and
leakage optimization, compatibility
with the design power grid, routabil-
ity, and pin accessibility. Covering
all of those library metrics requires
cell-level analysis as well as design-
context analysis, such as route trials.
A library cell may seem to have a high
quality at the cell level (for example,
fast performance and low power) but
may be low quality when used at the
design level. For example, if the cell
does not interact well with the design
power grid or if the router is unable to
access all of the cell pins, the design
tools will not take advantage of the
seemingly high-quality cell. If flaws
are identified early enough during the
design process, there is an opportu-
nity for cell layouts to be updated so
that they have high quality at both the
cell and design levels. Therefore, a
robust quality analysis of the library
requires parallel examinations at the
cell and design-context levels, result-
ing in a DTCO effort.
Library cell-level analysis consists
of evaluating the physical imple-
mentation of the cells as well as the
views generated to model the library
cells. Physical cell-level analysis can
be divided into two categories: 1) cell
architecture issues and optimizations
that can be applied to most cells in
the library and 2) cell-specific issues
and optimizations that can be applied
only to a single cell or small group of
cells. Architectural issues and opti-
mizations tend to be found first and
can often be automated with a layout
check on all cells. Cell-specific issues
and optimizations involve a more
focused effort on a subset of cells,
which often requires layout iterations

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