IEEE Solid-States Circuits Magazine - Fall 2019 - 66
technologies [15] and calculations for
7-nm and beyond [14].
Conclusions
With additional challenges for scal-
ing resulting from the possibility of
gate-all-around, tunnel field-effect
transistors, carbon nanotube, and
other new transistor options for
future nodes as well as the explo-
ration of new materials that could
impact the capacitance and resistance
of vias and interconnects, it is essen-
tial to have a framework to evaluate
early options between the designers
and the foundry to make the right
tradeoffs. Early access to the technol-
ogy and close collaboration are keys
to delivering high-performance, low-
power designs at the right cost points
to our customers.
References
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_nm_lithography_process
About the Authors
Kathryn Wilcox (Kathy.wilcox@amd
.com) received her B.S.E.E. from Cor-
nell University, Ithaca, New York, in
1990. She is a fellow on the CPU Core
team at AMD, Boxborough, Massa-
chusetts. Since joining the company
in 2003, she has worked on custom
circuit designs and the circuit design
methodology for many CPU cores. Her
research focuses on design technol-
ogy co-optimization, libraries, envi-
ronment, and methodology for future
CPU cores. She authored or coauthored
eight conference and journal publica-
tions. She served on the technical pro-
gram committees of the International
IEEE SOLID-STATE CIRCUITS MAGAZINE
Symposium on Low-Power Electronics
and Design, Symposium on Very-Large-
Scale-Integration Circuits, and Interna-
tional Solid-State Circuits Conference.
She is serving a three-year term on
the IEEE Solid-State Circuits Society
Administrative Comm it tee. She is
a Senior Member of the IEEE.
Lindsey Gentile (Lindsey.gentile@
amd.com) received her B.S. degree
in electrical engineering from North-
eastern University, Boston, Massa-
chusetts, in 2007. She is now an SMTS
silicon-design engineer on the CPU
Core team at AMD, Boxborough, Mas-
sachusetts. She joined the company
in 2007 and has worked on several
high-performance CPU core designs
in various physical-design roles.
Her experience includes static ran-
dom-access memory custom circuit
design, global circuit methodology,
synthesis place and route tile design,
and technology enablement for CPU
core projects. In recent years, she
has focused on standard cell library
development and optimization in
cutting-edge technologies to enable
high-performance and low-power
microprocessor designs.
Kevin Gillespie (kevin.gillespie@
amd.com) received his B.S. degree in
computer engineering from North-
eastern University, Boston. He is a
senior fellow on the CPU Core team
at A MD, Boxborough, Massachu-
setts, where he is the physical design
architect for a future CPU core, with
responsibility for performance power
projections as well as power and tim-
ing oversight, and the design leader
for foundry requirements across the
company, which he joined in 2003.
His previous experience includes
technical and managerial roles in
the development of multiple genera-
tions of x86 processors. Previously,
he worked at Digital Equipment and
contributed to CMOS virtual address
extension and alpha designs. His
research interests include technology
development, power optimization,
and design methodology.
https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/
https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/
https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/
https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/
https://en.wikipedia.org/wiki/Transistor_count
https://en.wikipedia.org/wiki/Transistor_count
https://en.wikipedia.org/wiki/Transistor_count
https://en.wikipedia.org/wiki/Transistor_count
https://en.wikichip.org/wiki/14_nm_lithography_process
https://en.wikichip.org/wiki/14_nm_lithography_process
IEEE Solid-States Circuits Magazine - Fall 2019
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2019
Contents
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