IEEE Solid-States Circuits Magazine - Fall 2019 - 66

technologies [15] and calculations for
7-nm and beyond [14].

Conclusions
With additional challenges for scal-
ing resulting from the possibility of
gate-all-around, tunnel field-effect
transistors, carbon nanotube, and
other new transistor options for
future nodes as well as the explo-
ration of new materials that could
impact the capacitance and resistance
of vias and interconnects, it is essen-
tial to have a framework to evaluate
early options between the designers
and the foundry to make the right
tradeoffs. Early access to the technol-
ogy and close collaboration are keys
to delivering high-performance, low-
power designs at the right cost points
to our customers.

References

[1] G. Northrop, "Design technology co-op-
timization in technology definition for
22nm and beyond," in Proc. 2011 Symp.
VLSI Technology-Digest Technical Papers,
Honolulu, HI, 2011, pp. 112-113.
[2] X. Wang et al., "Design-technology co-
optimization of standard cell libraries on
Intel 10nm process," in Proc. 2018 IEEE
Int. Electron Devices Meeting (IEDM), San
Francisco, 2018, pp. 28.2.1-28.2.4. doi:
10.1109/IEDM.2018.8614662.
[3] K. Vaidyanathan, L. Liebmann, A. Stro-
jwas, and L. Pileggi, "Sub-20 nm design
technology co-optimization for standard
cell logic," in Proc. 2014 IEEE/ACM Int.
Conf. Computer-Aided Design (ICCAD),
San Jose, CA, 2014, pp. 124-131. doi:
10.1109/ICCAD.2014.7001342.
[4] V. Vashishtha, A. Dosi, L. Masand, and L.
T. Clark, "Design technology co-optimiza-
tion of back end of line design rules for a 7
nm predictive process design kit," in Proc.
2017 18th Int. Symp. Quality Electronic
Design (ISQED), Santa Clara, CA, 2017,
pp. 149 -154. doi: 10.1109/ISQED.2017
.7918308.
[5] T. Huynh-Bao et al., "Design technology
co-optimization for enabling 5nm gate-
all-around nanowire 6T SRAM," in Proc.
2015 Int. Conf. IC Design Technology
(ICICDT), Leuven, Belgium, 2015, pp.
1-4. doi: 10.1109/ICICDT.2015.7165874.
[6] L. Bair, "P rocess/product interactions
in a concurrent design environment," in
Proc. 2007 IEEE Custom Integrated Circuits
Conf., San Jose, CA, 2007, pp. 779-782.
doi: 10.1109/CICC.2007.4405845.
[7] C. Hou, "A smart design paradigm for
smart chips," in Proc. 2017 IEEE Int. SolidState Circuits Conf. (ISSCC), San Francisco,
2017. doi: 10.1109/ISSCC.2017.7870240.
[8] C. Auth et al., "A 10nm high performance
and low-power CMOS technology featur-
ing 3rd generation FinFET transistors,
self-aligned quad patterning, contact
over active gate and cobalt local inter-
connects," in Proc. 2017 IEEE Int. Electron

66

FA L L 2 0 19

Devices Meeting (IEDM), San Francisco,
2017, pp. 29.1.1-29.1.4. doi: 10.1109/IEDM
.2017.8268472.
[9] J. Davis et al., "A 5.6GHz 64kB dual-read
data cache for the POWER6TM processor,"
in Proc. 2006 IEEE Int. Solid-State Circuits
Conf.-Digest Technical Papers, San Fran-
cisco, 2006, pp. 2564-2571. doi: 10.1109/
ISSCC.2006.1696322.
[10] H. Tomizawa et al., "Robust self-aligned
via process for 64nm pitch dual-dama-
scene interconnects using pitch split
double exposure patterning scheme," in
Proc. 2011 IEEE Int. Interconnect Technology Conf., Dresden, Germany, 2011, pp.
1-3. doi: 10.1109/IITC.2011.5940305.
[11] A. Yen, H. Meiling, and J. Benschop, "EUV
lithography at threshold of high-volume
manufacturing," in Proc. 2018 IEEE Int. Electron Devices Meeting (IEDM), San Fran-
cisco, 2018, pp. 11.6.1-11.6.4. doi: 10.1109/
IEDM.2018.8614502.
[12] W. Chen, "Heterogeneous integ ration
roadmap: Driv ing force and enabling
technology for systems of the future," in
Proc. 2019 Symp. VLSI Technology-Digest
Technical Papers, Kyoto, Japan, 2019.
doi: 10.23919/VLSIT.2019.8776484.
[13] Y. Ban, X. Zhu, J. Petykiewicz, and J. Zeng,
"Improving performance, power, and area
by optimizing gear ratio of gate-metal
pitches in sub-10nm node CMOS designs,"
in Proc. 2018 IEEE Symp. VLSI Technology,
Honolulu, HI, 2018, pp. 137-138. doi:
10.1109/VLSIT.2018.8510670.
[14] S. Jones, "7nm, 5nm and 3nm logic, current
and projected processes," SemiWiki, June 25,
2018. [Online]. Available: https://semiwiki
.com/semiconductor-manufacturers/intel/
7544-7nm-5nm-and-3nm-logic-current-and
-projected-processes/
[15] Wik ipedia, "Transistor count," 2019.
Accessed on: July 16, 2019. [Online].
Available: https://en.wikipedia.org/wiki/
Transistor_count
[16] WikiChip, "14nm lithography process." Ac-
cessed on: July 16, 2019. [Online]. Avail-
able: https://en.wikichip.org/wiki/14_nm
_lithography_process
[17] WikiChip, "10nm lithography process."
Accessed on: July 16, 2019. [Online]. Avail-
able: https://en.w ik ichip.org/wiki/10
_nm_lithography_process

About the Authors
Kathryn Wilcox (Kathy.wilcox@amd
.com) received her B.S.E.E. from Cor-
nell University, Ithaca, New York, in
1990. She is a fellow on the CPU Core
team at AMD, Boxborough, Massa-
chusetts. Since joining the company
in 2003, she has worked on custom
circuit designs and the circuit design
methodology for many CPU cores. Her
research focuses on design technol-
ogy co-optimization, libraries, envi-
ronment, and methodology for future
CPU cores. She authored or coauthored
eight conference and journal publica-
tions. She served on the technical pro-
gram committees of the International

IEEE SOLID-STATE CIRCUITS MAGAZINE

Symposium on Low-Power Electronics
and Design, Symposium on Very-Large-
Scale-Integration Circuits, and Interna-
tional Solid-State Circuits Conference.
She is serving a three-year term on
the IEEE Solid-State Circuits Society
Administrative Comm it tee. She is
a Senior Member of the IEEE.
Lindsey Gentile (Lindsey.gentile@
amd.com) received her B.S. degree
in electrical engineering from North-
eastern University, Boston, Massa-
chusetts, in 2007. She is now an SMTS
silicon-design engineer on the CPU
Core team at AMD, Boxborough, Mas-
sachusetts. She joined the company
in 2007 and has worked on several
high-performance CPU core designs
in various physical-design roles.
Her experience includes static ran-
dom-access memory custom circuit
design, global circuit methodology,
synthesis place and route tile design,
and technology enablement for CPU
core projects. In recent years, she
has focused on standard cell library
development and optimization in
cutting-edge technologies to enable
high-performance and low-power
microprocessor designs.
Kevin Gillespie (kevin.gillespie@
amd.com) received his B.S. degree in
computer engineering from North-
eastern University, Boston. He is a
senior fellow on the CPU Core team
at A MD, Boxborough, Massachu-
setts, where he is the physical design
architect for a future CPU core, with
responsibility for performance power
projections as well as power and tim-
ing oversight, and the design leader
for foundry requirements across the
company, which he joined in 2003.
His previous experience includes
technical and managerial roles in
the development of multiple genera-
tions of x86 processors. Previously,
he worked at Digital Equipment and
contributed to CMOS virtual address
extension and alpha designs. His
research interests include technology
development, power optimization,
and design methodology.

https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/ https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/ https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/ https://semiwiki.com/semiconductor-manufacturers/intel/7544-7nm-5nm-and-3nm-logic-current-and-projected-processes/ https://en.wikipedia.org/wiki/Transistor_count https://en.wikipedia.org/wiki/Transistor_count https://en.wikipedia.org/wiki/Transistor_count https://en.wikipedia.org/wiki/Transistor_count https://en.wikichip.org/wiki/14_nm_lithography_process https://en.wikichip.org/wiki/14_nm_lithography_process

IEEE Solid-States Circuits Magazine - Fall 2019

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2019