IEEE Solid-States Circuits Magazine - Fall 2019 - 85

intelligence, 5G, and CMOS technology
enablers. There was also a full-day
Friday forum, "Enabling Technologies for Autonomous Driving," that
included various presentations on
sensors, safety, security, and computing related to autonomous driving technologies.

Technical Milestones
The VLSI Symposia highlighted key
technical achievements in both the
paper presentation session and the
demo session. An exciting application
of sensor arrays built on a standard
130-nm CMOS process was presented
in "A 21,952-Pixel Multi-Modal CMOS

Vdd
Vb
GX,Y
(f)

16 mm

CNFET 2
ILD2

CNFET 1

ILD1

16 mm

ScreenOX

Si Diode
P ++

Si
(g)

(a)

9 mm
(b)

250 µm
(c)

15 µm
(d)

Drain

Source

what it would look like and whether
it will continue to grow as it has in
the past. One panel member, Bram
Nauta, mentioned the possibility that
some aspects of Moore's law could be
likened to progress in top aviation
speeds, which plateaued after the
1960s. Although the growth in some
technical aspects of aviation slowed,
significant progress in airplanes has
continued since the 1960s, including
efficiency, quality, cost, and safety
improvements. Nauta suggested that
enhancements in semiconductors are
very likely to continue, especially as
lithography, yield, and z-direction
(multiple layers) scale.
Panelist Shusaka Sumida noted
that the industry is experiencing a
transition from a von Neumann to a
non-von Neumann world in which
software and architecture enhancements will make up for any deceleration
on the semiconductor front. There has
been a recent explosion of artificial
intelligence funding that will likely
continue as machine learning establishes dominance in some markets. The
general opinion was that traditional
scaling will subside, but this was tempered by optimism in the future of the
semiconductor industry regarding
alternate scaling criteria.
In addition to the evening panel
discussions, there were opportunities
to learn outside of the paper presentation sessions, such as three short
courses on security and artificial

2.5 µm
(e)

A hybrid silicon-carbon-nanotube field effect transistor (CNFET) 3D imager revealed by MIT: (a) 3D
imager micrograph, (b) a magnified optical microscopy image of a subcircuit, (c) an edge-detector
logic block with a load CNFET, (d) a CMOS CNFET inverter, (e) a typical CNFET (3D model with a
scanning electron micrograph of a channel, false colored to match the model), (f) a schematic, and
(g) a 3D model of a silicon photodiode (layer 1, highlighted in blue) monolithically integrated with a
load CNFET (layer 2, highlighted in green) for transducing the pixel current output to an adjustable
voltage signal and a CMOS CNFET inverter (layer 3, highlighted in red) for digitizing the voltage
output from layer 2. Si: silicon.

The demo session and reception.

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IEEE Solid-States Circuits Magazine - Fall 2019

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