IEEE Solid-States Circuits Magazine - Fall 2020 - 10

1
800

Current (µA)

Voltage (V)

0.8
0.6
VY
VX
VP
VQ

0.4
0.2

600
400
200
0

0
300

350

400
Time (ps)

450

500

300

(a)

350

400
Time (ps)

450

500

(b)

FIGURE 5: The comparator's (a) voltage waveforms and (b) tail current waveform.

The speed of the comparator
depends on the input voltage difference, ultimately requir ing a
metastability analysis (as explained
later). However, it is common in ADC
design to select this difference to
be half of the least-significant bit,
which, in view of our tolerable offset, would be 10-20 mV for this design. However, we apply a difference
of 1 mV so as to place the circuit in
" slow motion " and examine its operation details. Plotted in Figure 5(a)
are the voltages at nodes P, Q, X,
and Y. The clock rises from zero to
VDD between t = 300 and t = 310 ps.
Note that VX and V Y experience a CM
drop of approximately 400 mV be-

fore they begin to depart as a result
of the regeneration provided by M5
and M 6. We also observe from Figure 5(b) that the tail current reaches
a peak of roughly 800 μA before VP
and VQ drop enough to drive the
input transistors into the triode region and cause the tail node voltage
to collapse.
F i g u r e 6 p l o t s VP - VQ f o r
Vin1 - Vin2 = 1mV. Two observations
prove important here. First, as shown
in the inset, VP - VQ reaches −3.15 mV
at t = 315 ps, the greatest difference
before M3 and M4 turn on. That is, the
initial voltage gain is equal to 3.15.
Second, VP - VQ is less than 100 μV at
t = 500 ps, i.e., before the next clock

0
-1
-2
-3
-4

0.1

Voltage (V)

0.05

305 310 315 320 325

0

-0.05

-0.1
300

350

400

450

Time (ps)
FIGURE 6: The difference between VP and VQ as a function of time.

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cycle. Thus, the precharge devices
are strong enough, and the dynamic
offset is negligible.
For design optimization, we need
a metric for the circuit's speed. For
example, we can find the time it
takes for | VX - VY | to reach a certain
amount, say, 200 mV. This time is
measured with respect to when the
clock's rising edge crosses VDD /2,
and is equal to 36 ps in Figure 5(a).

Offset and Speed Optimization
For the design in Figure 4, we must
quantify the input offset contributed by both the M3 and M4 pair
and the M5 and M 6 pair. To this end,
we place a voltage source equal to
DVTH3,4 = 4.4 mV in series with the
gate of M 3 while the other pairs
remain matched [Figure 7(a)]. We
then adjust the input voltage difference so that the circuit is nearly
balanced and VX - VY tends to stay
near zero for a relatively long time.
With some iteration, we find that
Vin1 - Vin2 . 1.15 mV leads to such a
behavior [see Figure 7(b)]. This suggests that the offset of M3 and M4 is
divided by a factor of 4.4/1.15 = 3.8
when referred to the input. The
offset standard deviation arising
from both the M1 and M2 pair and
the M3 and M4 pair is thus given by
(4.4 mV) 2 + (1.15 mV) 2 = 4.5 mV.
Given the small offset contribution of M3 and M4, we ask whether their
widths can be reduced so as to increase
the speed. Indeed, if W 3, 4 = 5 nm, then
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