IEEE Solid-States Circuits Magazine - Fall 2020 - 102

It is well known that both the alignment
patterns and process control patterns must
be inserted into the mask, which reduces
the number of fabricated dies on the wafer,
i.e., reduces GDW.
they do not discuss how to place the
die to achieve the estimated GDW.
Taking a closer look at the optimal
GDW estimation problem, we find
that there are actually two associated
problems: first, how to compute the
exact GDW for a given die placement
and, second, how the die should be
placed on the wafer to maximize
GDW. To understand these problems,
let us consider the wafer map presented in Figure 1. A foundry usually
handles wafers with standard size,
which is specified by the wafer diameter d. The wafer is handled with a
wafer holder, which covers up a portion of the wafer area, making it unusable. This unusable area is the area
covered by the ring, with the width
specified by wafer margin e from the
edge of the wafer, whereas the useful wafer area is the area covered by
the effective radius r = (d/2) - e. It

should be noted that, in most commercial wafers, the wafer is not a
perfect circular disk but has a flat
(as shown on the bottom of the wafer in Figure 1) that is made to ensure
the wafer placed within the foundry
machine will be oriented to align
the pattern to be fabricated with the
crystallographic direction of the wafer. This flat induces another unused
area with a depth of c + e (measured
from the edge of the wafer; see Figure 1),
where c is the maximum distance of
the unusable area from the edge of
the flat of the usable area along the
perpendicular line from the flat edge
to the disk center.
To simplify this discussion, we
define two lines running through
the center of the wafer, where the
angles between the two lines are all
90°, i.e., lines X and Y (see Figure 1),
as the two center axes of the wafer.

Models of Wafer Packing

r
Y

k th

b Die
kb
2nd
1st

c
Wafer Flat
d
Wafer Diameter

FIGURE 1: A typical wafer map, which shows the die placement on the wafer and its associated wafer dimensions.

FA L L 2 0 2 0

Our discussion of wafer packing begins with a description of the dieplacement model. The dies on the
mask are assumed to be rectangular
in shape with lengths of a and b on
the two sides, respectively, and are
arranged in a regular manner on the
mask (as demonstrated in Figure 1).
Based on this assumption, there are
several GDW estimations in the literature. The simplest is provided by
the ratio between the effective wafer area to the die area (where the
flat is ignored):

Wafer Margin

102

The silicon layout to be fabricated on
the wafer is known as the reticle, and
it may contain multiple designs (as
in the case of the multipurpose wafer process) and also other necessary
patterns (such as a scribe line, which
separates the design or the reserved
region for the wafer saw to be performed in between the designs and
so on). Commercially, the reticle is often simply called a die, which is used
in our discussion. It should be noted
that our discussion concentrates on
GDW estimation and on the density of
the dies that are packed (also known
as packing density) on the wafer without considering the set-up and postfabrication costs. Moreover, it is well
known that both alignment patterns
and process control patterns must be
inserted into the mask, which reduces the number of fabricated dies on
the wafer, i.e., reduces GDW. Because
the fabrication of the number of the
alignment patterns and process control patterns is very limited on the
wafer, it is at the same time deterministic and can be easily determined by
the machines used in the fabrication.
As a result, in order to simplify the
discussion in this article, we assume
that the area occupied by those patterns is negligible.

IEEE SOLID-STATE CIRCUITS MAGAZINE

2
GDW = ; r r E.(1)
a#b

This number is the upper bound of
the GDW. A better estimation can
be obtained by introducing a correction term that removes all of the

IEEE Solid-States Circuits Magazine - Fall 2020

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