IEEE Solid-States Circuits Magazine - Fall 2020 - 103
incomplete die around the boundary
of the wafer:
2
GDW = = r r a#b
Apart from the fact that these
GDW estimation formulas are not accurate, they are based on geometric
knowledge, which does not provide
any insight on how to place the die
on the wafer to achieve the largest
GDW. The die-placement-on-wafer
problem is related to 2D packing and
set-partition problems. If dies are allowed to be arbitrarily placed on the
wafer, the optimal die-placement
problem is proved to be nondeterministic polynomial-time (NP)-hard
[5]. Fortunately, to enable dies to
be sawed out easily, they are usually laid on the wafer with a regular
pattern. By means of regular placement and the symmetrical shape of
the wafer, the die placement must be
symmetric around the center axis
of the wafer. In other words, there
2rr
G,(2)
a2 + b2
where the second term is the ratio
of the circumference of the wafer to
the diagonal length of the die that
estimates the number of incomplete dies.
Another commonly applied GDW
estimation method that accounts
for the incomplete die around the
boundary of the wafer is to compute the effective wafer area with a
reduced radius by the estimated diagonal length of the die ( a # b ). As
a result, (1) is modified as
GDW = ;
(r - a # b ) 2 r
E.(3)
a#b
Y
a
Y
Q1
Q2
Q2
Q4
Q4
a
b
Q2
Q1
P1
X X
P2
Q3
Q3
Q4
x0
Q3
c
c
r
r
r
(a)
(b)
Y
(c)
a
Y
b
g
Y
b
a
Q2
Y
Q1
c
P2
Because of the symmetric-placement
constraint, only a limited set of dieplacement schemes are able to
achieve optimal GDW, and they are
all presented in Figure 2. The placement schemes are characterized by
how the die is aligned to the wafer,
which includes 1) how the die center
(also known as die centroid) is aligned
to the wafer center, 2) how the edge of
the die (known as die edge) is aligned
to either one or both center axes of
the wafer, and 3) how the die edge is
b
P3
X
Algorithm
a
P1
b
will be only a limited set of dieplacement schemes that might lead
to optimal GDW. In the following
section, we discuss each possible
die-placement schemes and its associated GDW.
P4
a
b
P1
Q1
P1
X
x0
Q4
X
X
x0
Q3
2
1
c
P3
(d)
r
P3
c
(e)
r
P2
c
(f)
r
FIGURE 2: Wafer packing with various die-placement schemes. (a) The die edge aligns with the wafer center; (b) the die center aligns with
the wafer center; (c) the die edge aligns with the wafer flat, and the other edge aligns with the wafer center; (d) the die edge aligns with the
wafer flat, and the die center aligns with the wafer center; (e) both die edges align with the flats of the wafer; and (f) irregular placement
with the die edge aligns with the wafer flat, and another edge aligns with the wafer center.
IEEE SOLID-STATE CIRCUITS MAGAZINE
FA L L 2 0 2 0
103
IEEE Solid-States Circuits Magazine - Fall 2020
Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020
Contents
IEEE Solid-States Circuits Magazine - Fall 2020 - Cover1
IEEE Solid-States Circuits Magazine - Fall 2020 - Cover2
IEEE Solid-States Circuits Magazine - Fall 2020 - Contents
IEEE Solid-States Circuits Magazine - Fall 2020 - 2
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