IEEE Solid-States Circuits Magazine - Fall 2020 - 104

aligned to either one or both of edge(s)
of the flat of the wafer.

Center Edge
This placement scheme positions
the die on the wafer such that both
of its edges are aligned to the two
center axes of the wafer by taking
the wafer center as the reference
point for the placement, as shown
in Figure 2(a). Hence, it is known as
a wafer-center-to-die-edge (centeredge) scheme. The wafer is divided
into four quarters (i.e., Q 1, Q 2, Q 3,
and Q 4) by cutting the wafer at lines
X and Y that go through the wafer
center. However, it should be noted that the number of rows in the
-upper two quarters and those in the
lower two quarters are different due
to the existence of the flat. In other
words, we compute the GDW of the
whole wafer by computing the number of complete dies in each quarter
independently and then summing
them up to obtain the final GDW.
The inset of Figure 1 illustrates the
generic placement of the die in the
upper-right quarter of the wafer,
which consists of k rows, with k being an integer. The dies are placed
one-by-one, with their edges packed
together and lined up from the origin of the quarter to the circumference of the useful radius and with
the subsequent row stacked on top
of the current one. It is easy to visualize that the same illustration can be
applied to other quarters by rotation,
which results in a different number
of rows. Let us first focus on the total number of dies in the upper-right
quarter of the wafer [denoted as Q 1, as
depicted in Figure 2(a)]. In the centeredge placement scheme, there are m
rows of dies in Q 1, where m is upper
bounded by
	

m = 8 r B.(4)
b

Let the total number of dies in this
quarter be N Q1, the sum of dies in
each row. Let us consider the triangle with height (opposite) b, and hypotenuse r, as shown in the inset of
Figure 1 (the triangle filled with solid

104	

FA L L 2 0 2 0	

white color). It is apparent that N Q1
is the lower bound of the floor adjacent to the triangle divided by a. By
means of the Pythagorean theorem,
the number of dies in the first row is
N Q1, 1, which can be obtained as
	

N Q1, 1 = ;

r2 - b2 E
.(5)
a

The number of dies in the second
row, N Q1, 2, can be computed by
considering the triangle filled with a
dotted pattern in the inset of Figure 1,
where the height of the triangle is
2b and the hypotenuse is r such
that the adjacent of the triangle is
r 2 - (2b) 2 , which yields
	

N Q1, 2 = ;

r 2 - (2b) 2 E
.(6)
a

In general, N Q1, k of the kth row of
dies is given by
	

r 2 - (kb) 2 E
N Q1, k = ;
.(7)
a

2
2
Hence, N Q1 = R m
k = 1 N Q1, k = 6 r - (kb) /
@
a . It should be noted that, due to
wafer symmetry along line Y, the total number of dies in Q 2 will be the
same as that of Q 1 (i.e., N Q1 = N Q2).
Note that the total number of rows
m in a quarter is given by

m=;

r2 - a2 E
.(8)
b
However, because a 11 r for most
cases, it is also safe to use the upper bound of m computed in (4) for
simplicity. Similarly, to take care of
the flat c in the lower half of the wafer, the number of dies n that can be
stacked in the lower half of the wafer
is upper bounded, which is given by
	

n = 8 r - c B.(9)
b

	

Furthermore, the total number of dies
in Q 3 is the same as in Q 4 and is given
by N Q3 = N Q4 = R nk = 1 6 r 2 - (kb) 2 /a@.
Putting everything together, the
GDW of the center-edge die-placement scheme can be computed as

	

N CE = N Q1 + N Q2 + N Q3 + N Q4
m
r 2 - (kb) 2 E

= / 2;
a
k=1
r - (kb) E
+ / 2;
.
a
k=1

IEEE SOLID-STATE CIRCUITS MAGAZINE	

n

2

2

Center Centroid
Another placement method that satisfies the symmetric constraint is
shown in Figure 2(b), where the wafer
center is taken as a reference point
and aligns with the die centroid in
such a way that the scheme is known
as the center-centroid scheme. The
same analysis as that presented in
the " Center Edge " section can be applied, where the wafer can be divided into four quarters by lines X and
Y, as displayed in Figure 2(b). However, there are incomplete dies on the
row and column overlapping lines X
and Y, respectively. Therefore, those
incomplete dies are first taken out of
the computation by introducing an
offset of 0.5a and 0.5b in the horizontal and vertical edges of the die,
respectively. Hence, we have
N Q1 = N Q2 =
2
2
m
/ ; r - ((k + 0a.5) b) - 0.5a E  (11)
k=1
and
N Q3 = N Q4 =
2
2
n
/ ; r - ((k + 0a.5) b) - 0.5a E, (12)
k=1
w h e r e m = 6r - 0.5b/b@ a n d n =
6^r - c - 0.5b h /b@. For the dies in
the shaded area of Figure 2(b), they
can be computed by summing up
the number of dies in regions P1, P2,
and P3, denoted as N P1, N P2, and N P3,
respectively, and are given by
	

N P1 = m + n + 1(13)

and
	 N P2 = N P3 = ;


r 2 - (0.5b) 2 - 0.5a E
,
a
(14)

respectively. As a result, the GDW
of this placement scheme, N CC , is
given by
N CC = N Q1 + N Q2 + N Q3 + N Q4 + N P2
+ N P3 + N P1
m
r 2 - ((k + 0.5) b) 2 - 0.5a E
= / 2;
a
k=1
r - ((k + 0.5) b) - 0.5a E
+ / 2;
	
a
n

2

2

k=1

(10)

+ 2;

r 2 - (0.5b) 2 - 0.5a E
a
+ m + n + 1.

(15)
IEEE Solid-States Circuits Magazine - Fall 2020

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