IEEE Solid-States Circuits Magazine - Fall 2020 - 105

Flats
Flats refer to the cuts on one or more
sides of the wafers to indicate their
crystallographic planes or doping
types. This section focuses on the
placement scheme for wafers with a
single flat, while the " Two Flats " section considers the case of two flats.
If c is large when compared to b, it
will be better to align the die edge
with the flat edge to minimize the
number of incomplete dies along
the wafer flat. There are two ways
to place dies with edges aligned to
the wafer flat without violating the
constraint on placement symmetry;
these include 1) aligning the die edge
to the flat edge (referred to as edge
flat) and 2) aligning the die centroid
to the flat edge (also known as centroid flat), as depicted in Figure 2(c)
and (d), respectively. Both alignment
schemes make reference to the flat
edge; therefore, incomplete dies
would be observed along lines X and
Y when the same quarter model (the
inset of Figure 1) is considered for
GDW computation, which is similar
to that discussed in the center-centroid scheme. Nonetheless, because
the reference is made upon the flat
edge, there would be an offset x 0
from line X to the die-centroid of
those dies sitting on line X [as illustrated in Figure 2(c) and (d)]. The
value of x 0 depends on the values of
r, c, and b, expressed as
	

x 0 = r - c - 8 r - c B b.(16)
b

The following two sections consider
the GDW of the edge- and centroidflat placement schemes.

to compute the GDW N EF of the edgeflat placement scheme by adjusting
(10) with a vertical offset x 0 such
that (11) and (12) are rewritten as
N Q1 = N Q2 =

/;
m

k=1

r 2 - (kb - x 0) 2 E
(17)
a

This placement scheme aligns one
die edge to the flat edge while having the other die edge aligned with
line Y. Therefore, we can divide the
wafers into four quarters, that is, Q 1,
Q 2, Q 3, and Q 4, and a row containing the dies that cannot be computed
by the quarter model P1 [see Figure
2(c)]. Similar to the GDW computation in the case of center-centroid
placement, we can make use of (10)

of 0.5a along the direction of line X.
Similarly, there is an offset x 0 from
line X to the die centroid for those
dies sitting on line X. Hence, modifying the equations of the edge-flat
placement scheme to accommodate
the 0.5a displacement yields

and
	 N Q3 = N Q4 = / ;
k=0

n

r 2 - (r - c - kb) 2 E
,
a
(18)

w it h m = 6^r - b + x h /b@ a n d n =
6^r - c h /b@ as the number of rows of
complete dies above and below line
X, respectively, and x 0 depicted in
(16). The number of dies on the row
that overlaps with line X of the wafer, enclosed in P1, is given by
P1 =
Z
r 2 - x 20 E
]
2;
if 0.5b 1 x 0 1 b, 	
	]
a
[
2
2
		
]] 2 ; r - (b - x 0) E if 0 1 x 0 # 0.5b.
a
	
\
(19)
As a result, the N EF for edge-flat
placement is given by

N Q1 = N Q2 =
2
2
m
	
/ ; r - (kb -ax 0) - 0.5a E  (21)
k=1
and
N Q3 = N Q4 =
2
2
n
/ ; r - (r - c -a kb) - 0.5a E, (22)
k=0
where
n=
m = 6^r - b + x h /b@,
6^r -c h /b@, and x 0 are the same as in
(16). The number of dies on the row
that overlaps with line X of wafer P1 is
given (23) at the bottom of this page.
As a result, the GDW of the centroid-flat placement scheme, N CF , is
given by
N CF = N Q1 + N Q2 + N Q3 + N Q4 + P1,
m
r 2 - (kb - x 0) 2 - 0.5a E
= / 2;
a
k=1

N EF = N Q1 + N Q2 + N Q3 + N Q4 + P1,
	
2
2
n
2
2
m
; r - (r - c - kb) - 0.5a E
			
(
r
kb
x
+
2
/
0)
E
	
= / 2;
a
k=0
a
	
k=1
			
+
P
,
(24)
1
n
r 2 - (r - c - kb) 2 E
			
+ / 2;
+ P1,
a
k=0
where P1 is depicted in (23).

(20)
where P1 is depicted in (19).

Centroid Flat

Edge Flat

	

Flats refer to the cuts on one or more sides of
the wafers to indicate their crystallographic
planes or doping types.

The centroid-flat placement scheme
illustrated in Figure 2(d) is a variation of the edge-flat scheme with the
die centroid that coincides with line
Y, which introduces a displacement

	

Two Flats
When the wafer has two flats, the
best die placement should align both
die edges with both flat edges, as
displayed in Figure 2(e). This figure
also shows a dummy die that helps
form a rectangular placement over
the wafer to compute the GDWs. The

Z
r 2 - x 20 - 0.5a E
]
2;
,
if 0.5b 1 x 0 1 b,
]
a
P1 = [
(23)
2
2
]] 2 ; r - (b - x 0) - 0.5a E, if 0 1 x 0 # 0.5b.
a
\

	 IEEE SOLID-STATE CIRCUITS MAGAZINE	

FA L L 2 0 2 0	

105
IEEE Solid-States Circuits Magazine - Fall 2020

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