IEEE Solid-States Circuits Magazine - Fall 2020 - 116

SSCS Distinguished Lecture on the Evolution
of Cellular Radio-Frequency ICs

The IEEE Solid-State Circuits Society (SSCS) Switzerland Chapter organized a Distinguished Lecture
webinar on 25 June 2020. The event
featured Dr. Venumadhav Bhagavatula, senior staff engineer, Samsung
Semiconductors, San Jose, California. The Chapter invited Bhagavatula to speak about the evolution of
cellular radio-frequency ICs (RFICs),
from 2G to 5G. The event was part of
the Chapter's first-quarter program
regarding communications circuits,
including millimeter-wave (mmwave) 5G, and another lecture was
planned for later in the summer.
The event took place online via
the WebEx services IEEE provides
to local Chapters (Figure 1). It was
advertised through IEEE eNotice [1]
within the Switzerland Chapter and
other Region 8 Chapters. The audience included 36 IEEE Switzerland
Chapter members, two nonmembers, and roughly 20 members from
Region 8. The organizers extend
special thanks to the United Kingdom Chapter.
The talk was divided into five
subparts and discussed the transmitter (Tx) and receiver (Rx) path
challenges of each generation of
the cellular standard. Per the introduction, Bhagavatula illustrated
his talk with a transceiver block
diagram followed by actual smartphone motherboards where plenty
of silicon devices sit, among which
one recurring part is the RFIC. For
the noninitiated, a brief review of
sensitivity, noise figure, intermodulation, reciprocal mixing, and phase
noise was prepared (Figure 2).
Essentially, in the 2G standard,
the Tx and Rx paths operate at different times and frequencies. From
the circuit perspective, this can
improve the isolation between the

two paths. Nevertheless, within two
adjacent cells, multiple parties may
simultaneously use the infrastructure; thus, one handheld device
may disturb another, corrupting the
second's received information. This
is known as the near-far problem.

2G Tx Noise in an Adjacent Rx Band
Going forward with the near-far
problem, Rx noise desensitization imposes a requirement that
the noise at 20 MHz must be -165 dB
relative to the carrier (dBc)/Hz.
Considering a direct-conversion
in-phase/quadrature architecture,

half the noise budget is allocated
to the signal path, and the remainder is assigned to the clock path.
The clock phase noise increases by
12 dB before the division four operation. This translates into a very
challenging constraint of -156 dBc/
Hz at 20 MHz. A key insight from
Leeson's expression [2] is that increasing the signal swing and raising the tank quality factor by 2×
result in a 6-dB improvement to the
phase noise. Using back-of-the envelope calculations, the derivations
made in [3] show that the supply
voltage escalates in scaled CMOS

FIGURE 1: Participants gather for Dr. Venumadhav Bhagavatula's WebEx lecture.

Digital Object Identifier 10.1109/MSSC.2020.3021933
Date of current version: 18 November 2020

116

FA L L 2 0 2 0

FIGURE 2: Attendees discuss the material with Dr. Bhagavatula.

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IEEE Solid-States Circuits Magazine - Fall 2020

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