IEEE Solid-States Circuits Magazine - Fall 2020 - 13

input difference of 1 mV, 100 μV, and
10 μV, thus arriving at the waveforms
shown in Figure 13. The time shift in
each case is 5.7 ps and implies that
x reg = 5.7 ps/ ln 10 = 2.5 ps.
Can we reduce x reg by adjusting t he w idt hs of M 5 a nd M 6 in
Fig ur e 4? If W 5, 6 is doubled, these
two devices' capacitances double,
but their transconductance rises by
roughly a factor of 2 . That is, x reg
decreases only if M5 and M 6 do not
dominate the capacitance at X and
Y. In our design, changing W 5, 6 from
2.5 to 5 μm increases x reg slightly.
The foregoing observations prescribe
a simple method for estimating the input difference VXY0 in (3), which leads to
an error. We first simulate the comparator with a moderate value for Vin1 - Vin2,
e.g., 1 mV, and find the delay, e.g., 22 ps.
We also recognize that 1) reducing
Vin1 - Vin2 by a factor of 10 n shifts the
response by nx reg ln 10 and 2) if the
shift exceeds TCK /2 - 22 ps, an error is
likely to occur. In our design,
	

nx reg ln 10 .

	

0.8

Voltage (V)

VX
VY

0.6

VX
VY

0.4

VX
VY

0.2

0
300

320

340
Time (ps)

FIGURE 13: The output waveforms of the comparator for input differences equal to 1 mV,
100 μV, and 10 μV.

This means that the capacitances seen
at the inverters' inputs are also slightly unequal (due to the Miller effect of
their gate-drain parasitics). This deterministic imbalance causes the StrongArm latch to favor one logical output
for very small input differences. We
therefore disconnect the RS latch for
such simulations. Alternatively, we can
short A and B to VDD so as to maintain
the loading presented to the inverters.
Another metastability simulation
issue relates to the simulator's accuracies. In Cadence, we set three
parameter as follows: reltol = 10 -6,
vabstol = 10 -6, and iabstol = 10 -12 .

TCK
- 22ps ,(7)
2

. 78 ps (8)

and, hence, n . 13.5. It follows that
input differences of <1 mV/10 13.5
may generate errors.
We should remark that simulating a
comparator with very small input differences, e.g., 1 fV, requires minimizing all the sources of asymmetry in the
circuit and in the simulation tool. Specifically, the presence of the RS latch in
Figure 9 does lead to a slight asymmetry in the StrongArm circuit. Suppose
the stored state is VA = 0 and VB = VDD.
As a result, the gate input capacitances
of M11 and M12 are slightly different.

comparator's time-domain decision
is randomly affected by the noise of
its constituent devices. We first set
Vin1 - Vin2 to zero [Figure 14(a)] and
ensure that the logical output assumes
a value of zero or one with equal probabilities. Plotted in Figure 15(a) are
VX and VY, in this case, for 100 clock
cycles. We observe that VX goes to zero
approximately 50 times.
Next, we select a small, constant
value for | Vin1 - Vin2 | so as to skew the
decisions [see Figure 14(b)]. We recall
that the area under a Gaussian distribution from - v to + v is equal to
68% and hence that from - 3 to - v
is 100% - (34% + 50%) = 16%. Thus, if
VS is chosen so as to reduce the probability of zeros to 16%, then VS = v,
which is also the total root-meansquare (rms) noise referred to the input. After a few iterations, we observe
the waveforms in Figure 15(b), where
VX goes to zero roughly 16 times for

Input-Referred Noise
The standard method of computing
the output noise and dividing it by the
gain does not apply to comparators
because they produce a digital output. As explained in [4], we perform a
transient noise simulation so that the

fX(x )

fX(x )
Probability of
Ones

Probability of
Zeros

Vout
CK
(a)

360

0

VS

+
-

Vout
CK

x

(b)

Probability of
Zeros

Probability of
Ones

-VS 0

x

FIGURE 14: (a) A perfectly balanced comparator generates ones and zeros with equal probabilities; (b) a finite input imbalance
skews the decisions.

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IEEE Solid-States Circuits Magazine - Fall 2020

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