IEEE Solid-States Circuits Magazine - Fall 2020 - 14

1.2
VY
VX

Voltage (V)

1
0.8
0.6
0.4
0.2
0
-0.2

0

2

4

6

8

10
Time (ns)
(b)

12

14

16

18

20

1.2
VY
VX

Voltage (V)

1
0.8
0.6
0.4
0.2
0
-0.2

0

2

4

6

8

10
Time (ns)
(a)

12

14

16

18

20

FIGURE 15: The comparator outputs (a) for perfect balance and (b) with an input difference equal to 0.31 mV.

200

Iin1
Iin2

150

Current (µA)

100
50
0
-50

and the latter prove problematic generally. Kickback noise trades with the
dimensions of the input transistors
and hence with the offset voltage. But
the timing of this noise determines
whether it has an adverse effect on the
performance. For example, we expect
the noise around t = 300 ps in Figure 16 to be more serious, as it coincides
with the comparator's decision time.

-100

References

-150
-200
300

350

400
Time (ps)

450

FIGURE 16: The input kickback noise currents of a StrongArm comparator.

VS = 0.31mV. The comparator's input rms noise is approximately equal
to this value. For greater precision,
we can run the two simulations for a
larger number of clock cycles.

Kickback Noise
The StrongArm latch draws large transient currents from its inputs during
switching. Called the kickback noise,
this phenomenon proves undesirable
if it affects the comparator's own deci-

14	

FA L L 2 0 2 0	

sion or corrupts the input voltage while
it is sensed by other circuits. For example, in a flash ADC, all of the comparators generate kickback noise while one
must make a critical decision. Figure 16
plots the kickback noise currents of
our design when Vin1 - Vin2 = 1mV.
The clock begins to rise at t = 300 ps.
We recognize that the two exhibit both
CM and differential components. The
former are objectionable if they flow
through unequal source impedances,

IEEE SOLID-STATE CIRCUITS MAGAZINE	

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