IEEE Solid-States Circuits Magazine - Fall 2020 - 17

Vout
( jω) (dB)
Vdd
gmRL

VREF

+
-

1/A0

CA M
n
A

+
VDropout
-

vout (t ) = VREG

ω0 << ωL
ω
ω0
Vout
( jω) (dB)
Vdd

ωL << ω0
ω
(b)

FIGURE 6: The ripple transfer function under
two design scenarios for (a) when ~ 0 % ~ L
and (b) when ~ L % ~ 0.

To see what portion of v dd is
transferred to the output, we redraw
a small-signal equivalent model of
the regulator of Figure 4 in Figure 5(a),
clearly illustrating the negative
feedback employed by this circuit.
The corresponding block diagram in
Figure 5(b) includes the effect of the
poles associated with the load (~ L)
and with the error amplifier (~ 0).
The input to this block diagram is
the ripple on the power supply (Vdd),
and the output is the corresponding ripple at the output node (Vout).
For simplicity, we treat the ripple
as a deterministic signal, i.e., not a
random signal. Let us now write an
expression for the transfer function
from Vdd to Vout:
gm RL
1+ s
Vout ^ h
~L
.
s =
Vdd
gm RL
A0
1+
1+ s 1+ s
~L
~0
Before simplifying this equation,
let us make a quick observation here:
at dc (i.e., when s = 0), the gain from
the power supply ripple to the output is given by g m R L / (1 + g m R L A 0),
which is approximately equal to
1/A 0 if we assume g m R L A 0 & 1. This

	

CL

FIGURE 7: An NMOS transistor is employed as a controlled current source in a regulated
voltage supply, as shown in Figure 3.

1/A0

ωL

RL

ω0 (1 + gmRLA0)
(a)

is great because it shows that the circuit clearly attenuates any dc ripple
by a factor of 1/A 0. The larger the
A 0, the smaller portion of the ripple
that infiltrates the output. For the
frequency-dependent attenuation of
the ripple, we consider two design
choices. The first one is to make ~ 0
dominant, i.e., ~ 0 % ~ L. In this case,
for frequencies much lower than ~ L,
we can treat s/~ L as 0 and simplify
the previous equation as
Vout ^ h
s , 1
Vdd
A0 1 +

is g m R L. As we further increase the
frequency, the output pole will kick
in, and the overall transfer function
begins to drop again.
A second design choice is to
make ~ L dominant, i.e., ~ L % ~ 0. In
this case, we can ignore s/~ 0 for all
frequencies much smaller than ~ 0
and write
Vout ^ h
s , 1
A0 1 +
Vdd

1+ s
~0
.
s
~ 0 ^1 + g m R L A 0h

1

s
~ L ^1 + g m R L A 0h

.

In this scenario, the transfer
function sees the dominant pole
first as we increase the ripple freThis transfer function has a zero
quency; the zero will be at a much
at ~ 0 and a pole at a higher frehigher frequency. As a result, the
quency, implying that a larger pormagnitude of the transfer function
tion of the ripple will transfer to
drops after the dominant pole, as
the output for the ripple frequencies
depicted in Figure 6(b). To see this
in between the zero and the
intuitively, imagine
pole frequencies. A sketch of
that the error ampliSince ~0 is
the Bode plot of this transfer
fier has a constant
dominant, as
function is shown in Figgain independent of
soon as we
ure 6(a). Let us now see intuif r e q u e n c y. Then we
increase the
tively why the gain increases
can simply replace A
ripple frequency
with A 0 (this is indeed
beyond dc and why it falls
beyond ~0 ,
the case for frequencies
at larger frequencies. Since
the gain of the
error amplifier
~ 0 is dominant, as soon as
below ~ 0). In this case,
becomes smaller,
we increase the ripple frewe simply have a low-pass
and
the feedback
quency beyond ~ 0, the
filter with a single capacibecomes
gain of the error amplifier
tor (C L) at the output node,
ineffective.
becomes smaller, and
reducing the output voltage
the feedback becomes
as a function of frequency.
ineffective. In the limit, if the error
In the preceding arguments, we
amplifier gain A becomes much
have clearly ignored the analysis at
smaller than 1, then the gate of the
higher frequencies, where none of s/~ 0
and s/~ L can be ignored. The good
PMOS transistor in Figure 4 can be
news is that, under the first scenario, the
considered ground (zero feedback).
transfer function may only drop furIn this case, the gain from Vdd to Vout
will be at its maximum value, which
ther due to a higher-frequency pole;

	 IEEE SOLID-STATE CIRCUITS MAGAZINE	

FA L L 2 0 2 0	

17
IEEE Solid-States Circuits Magazine - Fall 2020

Table of Contents for the Digital Edition of IEEE Solid-States Circuits Magazine - Fall 2020
