IEEE Solid-States Circuits Magazine - Fall 2020 - 29

200 GHz, due to process and design
advancements. Because of the closeby operating frequency compared to
the device cutoff frequencies, conventional low-noise amplifiers do
not gain edges with a high power
consumption and a high NF. To overcome the limitations of conventional
approaches, a novel idea termed the
self-oscillating mixer was investigated and demonstrated good results
with an NF of 21.2~23.5 dB and an
intermediate frequency bandwidth of
22-30 GHz [100]. Besides, coherent
receivers demonstrate better noise
performance than the direct-detection and noncoherent variants [93],
[99], and they have higher front-end
signal gains to suppress the subsequent circuit noise.
To support coherent receivers,
synthesized clocks are required. Highfrequency synthesizer developments
have also significantly advanced
during the past decade. A 560-GHz
CMOS synthesizer is developed with
a 21-GHz locking range and a phase
noise below -74 dB relative to the carrier (dBc)/Hz at a 1-MHz offset [101].
To solve the high-frequency local
oscillator (LO) distribution problem,
a novel decentralized architecture is
invented for high-density and largescale array scenarios, with two interleaved 4 × 4 arrays driven by a locked
240-GHz LO with a phase noise of
-84 dBc/Hz at a 1-MHz offset [102].
Both designs are implemented in a
65-nm CMOS.
In terms of applications, siliconbased integrated sub-THz/THz imaging and sensing and spectroscopy
have been intensively investigated
[103]-[105], and good review articles
for different applications can be found
in [93] and [106]. Due to the large
fractional bandwidth, it is natural to
adopt sub-THz/THz approaches for
wideband communication, both wireless and wireline. For example, at a
300-GHz carrier, a 128-quadratureamplitude-modulation, 21-gigabaud
transmitter in a 40-nm CMOS is published to support an overall 105-Gb/s
data rate [107]. A CMOS-based wireless
communication system at 217 GHz is

As opposed to other applications, energy
efficiency is the king for actives in interconnect
applications, and it should be the first priority.
also successfully demonstrated for
the link distance of 10 cm, with an
energy efficiency of 37 pJ/b [108].
However, wireless communication
faces a fundamental power challenge
due to free space loss, based on the
Friis propagation loss model. For example, a 1-m free space path loss is
approximately 82 dB at 300 GHz, thus
demanding significant transmitter
output power and little receiver noise
and degrading energy efficiency. For
example, a 100-cm wireless communication with a 65-Gb/s data rate at a
225-GHz carrier frequency is reported. The energy efficiency is roughly
30 pJ/b, with a BER of 10−3 [109]. To
extend the communication distance
beyond 1 m, the 20-dB-greater loss
would require at least 100× more power consumption, prohibiting adoption
in low-power portable wireless communication and power- and cost-sensitive interconnect applications.
Therefore, to avoid free space path
loss, low-loss-media-based wireline
communication is an option to possibly achieve high energy efficiency
for interconnects. For example, plastic
waveguide-based wireline links achieve
a data rate of 6.2 Gb/s, with a very good
energy efficiency of 11.7 pJ/b across a
record distance of 8 m [110], [111], and
a low-loss DWG-based 130-GHz transmitter achieves a 36-Gb/s data rate and
an energy efficiency of 6 pJ/b [112]. To
boost energy efficiency for interconnect applications and be scalable with
rising data rate requirements, subpicojoule-per-bit THz interconnect systems
based on silicon DWGs have also been
demonstrated [91].

Energy Efficiency is King for
Sub-THz/THz Interconnects
Interconnect application is extremely
sensitive to costs and power consumption; therefore, mainstreambased silicon processes, particularly
the CMOS, are the ones to use. Even

with that, the trend that every 10×
performance improvement costs 1.5×
more and consumes 2× more power
[113] impedes interconnect advancements and scalability with everincreasing data rate requirements. In
particular, the power consumption
density is the hard limit for silicon,
due to the material's finite thermal
conductivity and limited thermal
control and mitigation approaches.
Thus, as opposed to other applications, energy efficiency is the king
for actives in interconnect applications, and it should be the first priority. With that, a few takeaways can be
summarized when designing active
circuits and systems for interconnects,
including the following:
■■ Do not trade energy efficiency for
other specifications, such as output power and noise performance.
Output power and noise performance can be enhanced through
other approaches, such as the array
structure, and they can be forgiven
due to low-loss channels and novel
transceiver architectures.
■■ Due to device limits, fundamental
frequency generation and amplification are subject to a trend where
the power generation drops by
20 dB/decade [44] and the NF dauntingly increases by roughly 20 dB/
decade, w ith NF &1 [47 ], [48].
Correspondingly, the efficiency
drops to approximately 1%/decade.
Therefore, the frequency choice
is critical to boost energy efficiency while increasing bandwidth density. First, the frequency needs to be in the range of
the device capabilities for highpower efficiency and low-noise
performance. Second, it should
be higher within the device
capability so that the passive
and channel sizes are smaller
to produce a greater bandwidth
density.

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