IEEE Solid-States Circuits Magazine - Fall 2020 - 50

Synthesis
(46%)
Perl (77%)

System
Verilog (38%)

Verilog (69%)

A Case Study
Modern SoCs, particularly those
targeting machine learning applica-
tions, incorporate a large and grow-
ing number of specialized hardware
units to efficiently execute specific
tasks. With advances in machine
learning algorithms during the past
decade, compute requirements are
outpacing advances from Moore's law
such that hardware must be flexible
and future-proofed for new applica-
tions. Yet the traditional IC design
cycle can take many months to sev-
eral years from specification to get-
ting the first silicon in the lab for
tests. This is not fast enough to keep
pace with domain-specific algorithm
design, so new methodologies need
to be incorporated for true hardware/
software codesign.
Recently, at NVIDIA, a small research
team designed an 87-million-transistor

Timing
Closure
(38%)
C/C++/
SystemC
(23%)

Python (69%)

Verification
(UVM, SVA)
(54%)

tap into the huge ranks of students
studying those fields. Unique solu-
tions to problems often lie at the inter-
section of disciplines, so should we
move toward an interface with soft-
ware to accelerate innovation?

TCL (38%)

MATLAB
(23%)
Power
Extraction
(23%)

Shell
Scripting
(38%)

Linting
(31%)

HLS (23%)
DRC/LVS
(15%)
VHDL
(15%)
SKILL
(15%)

UPF
(15%)

MBIST/
P&R DFT
(15%) (15%)
Spectre/
HSPICE
(15%)

toward higher levels of abstraction
at top circuits conferences, such as
the International Solid-State Circuits
Conference and the Symposia on
VLSI Technology and Circuits, where
there has been an increase in system
on chip (SoC)-level and domain-spe-
cific processing papers as electronic
design automation (EDA) tools have
become more mature and ubiquitous.
If this trend toward software-based
design continues for years to come,
it has the potential to reduce the size
of the talent pool from which we can
recruit new circuit designers for the
field. Yet the problem is not a zerosum game, as working across the hard-
ware/software interface in computing
is common. If we borrow concepts
from software engineering to improve
circuit design practices and increase
the breadth of the problems solved
within circuits, we can both improve
design productivity and lower the bar-
rier to entry for chip design, making
the field more accessible and improv-
ing the potential for high-value inno-
vation. Additionally, if IC design could
integrate concepts from software devel-
opment, the field could more readily

LEF
(8%)
Virtuoso
(8%)

FIGURE 2: Survey results for the desired skills/tools required for ASIC design positions across
many semiconductor company job posts. Skills traditionally associated with the software
community are in red, while those typically associated with the chip design community are in
blue. SVA: SystemVerilog assertions; TCL: Tool Command Language; HLS: high-level synthesis;
DRC/LVS: design rule check/layout versus schematic; MBIST/DFT: memory built-in self-test/
design for test; VHDL: very high-speed IC hardware description language; UVM: universal
verification methodology; UPF: unified power format; P&R: place and route; LEF: library
exchange format.

50	

FA L L 2 0 2 0	

IEEE SOLID-STATE CIRCUITS MAGAZINE	

inference accelerator chip [4] that
can be tiled on package for scalable
performance in machine learning
applications. Many of the productivity
gains we realized during the design
process were concepts and tech-
niques that originated in the software
community, including using a high--
productivity design methodology, a
high-level language as the hardware
description language (HDL), and a
highly parameterizable open source
design library to improve reuse.
The inference accelerator was de--
signed with a high-productivity VLSI
flow that enabled a 24-h turnaround
from a design change to a tapeout ready
graphic design system (GDS). Most of
the design was described in C++ using
the MatchLib [5] open source library
of common microarchitectural com-
ponents and synthesized into Ver-
ilog through an industry-standard
high-level synthesis (HLS) tool. The
design was intentionally modular-
ized into partitions of roughly 200,000
gates, which avoids tight timing con-
straints among units by using latency--
insensitive (LI) channels.
The main partitions in the design
are the processing element (PE),
global buffer (GB), RISC-V processor,
network-on-package (NoP), and ground
reference signaling (GRS) units, as
annotated in the floorplan in Figure 3.
Each was implemented independently
and in parallel with the others to
improve the design turnaround time.
Partitioning the design into smaller
units raises the number of cross-unit
boundaries, while larger units increase
the place-and-route runtime. An agile
hardware implementation flow using
fully automated synthesis and placeand-route tools provided daily feed-
back about the timing, area, and power
consumption as the design was opti-
mized. The reduced time costs of par-
tition-level respins, due to the limited
partition size, enabled engineering
change orders (ECOs) to be avoided
entirely by making alterations directly
in the source code and reimplement-
ing the full unit.
To further improve design pro-
ductivity and turnaround time, each
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