IEEE Solid-States Circuits Magazine - Fall 2020 - 51

partition has a separate clock domain,
removing the need for full-chip tim-
ing closure and further saving energy
under varying computational loads.
In this approach, a design is broken
into many small, synchronous clock
domains, each of which operates on
an independently generated clock.
Since each domain is asynchronous
relative to the others, its clock can
be tuned independently. Thus, the
timing margin is reduced, as each
domain operates at a frequency best
suited to local conditions. By restrict-
ing synchronous timing paths to
smaller clock domains, the challenge
of timing the closure at higher lev-
els of the design hierarchy is entirely
eliminated; small changes to a parti-
tion netlist impact only the timing
and layout of that partition and not
the entire system [7]. This partitionlevel clocking modularity is enabled
by LI interfaces at all of the parti-
tion boundaries.

GRS WRX

Agile Development
Tapeouts are known for being stress-
ful, as last-minute and unpredictable
issues always seem arise. It often

GRS NTX

2.5 mm

The growing complexity of chips
designed by small teams, such as this
inference accelerator, includes inno-
vations in architecture, packaging,
and circuits. This has led to a produc-
tivity crisis, stimulating development
of new tools and methodologies to
enable the creation of complex chips
on schedule and within budget. For
our inference accelerator design, over-
lapping architectural exploration/
specification, VLSI implementation,
and software design ensured that
effort was focused on improving the
final quality of the result. The circuitlevel innovations are discussed in [4],
but many of the improvements in the
chip design process are inspired by
software development trends and dis-
cussed in the following sections.

RVP

GPIO

GRS NRX

appears nearly impossible to suffi-
ciently guard-band schedules to leave
time for dealing with these issues
while still making the deadline. Soft-
ware projects typically have the lux-
ury of addressing bugs and adding
features through patches and multi-
ple code rollouts, easing the cost of a
mistake in the code and the pressure
to produce feature-complete designs.
In the best-case scenario for chip
designers, bugs can be fixed with
firmware and software patches, but
correcting flaws more often requires
mask changes and respins of an entire
design, costing both time and signifi-
cant resources. This high(er) cost of
bugs motivates a design philosophy
and set of procedures intended to
minimize the chance of mistakes.
The traditional approach to chip
development is a waterfall design
methodology, as shown in Figure 4. This
technique serializes the steps in the
design process such that a subsequent

GRS ETX

NoP

(b)
GRS WTX

GRS SRX

JTAG

GRS STX

GRS ERX

2.4 mm
(a)
FIGURE 3: (a) The chip micrograph of the inference accelerator chip is highly scalable and (b) assembled as a 36-die system. GPIO:
general-purpose input-output. WRX: west receiver; NTX: north transmitter; ETX: east transmitter; SRX: south receiver; STX: south transmitter;
ERX: east receiver; JTAG: Joint Test Action Group.

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IEEE Solid-States Circuits Magazine - Fall 2020

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